Add clock generation for the mig
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589e9960c0
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@ -114,6 +114,17 @@ class ml507_dvi_clock extends BlackBox {
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}
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}
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}
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}
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class ml507_ddr2_clock extends BlackBox {
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val io = new Bundle {
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val CLKIN_P_IN = Clock(INPUT)
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val CLKIN_N_IN = Clock(INPUT)
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val CLK0_OUT = Clock(OUTPUT)
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val CLK90_OUT = Clock(OUTPUT)
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val CLKDV_OUT = Clock(OUTPUT)
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val LOCKED_OUT = Bool(OUTPUT)
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}
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}
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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// vc707_sys_clock_mmcm
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// vc707_sys_clock_mmcm
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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@ -16,7 +16,7 @@ import sifive.blocks.devices.chiplink._
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import sifive.blocks.devices.terminal._
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import sifive.blocks.devices.terminal._
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import sifive.fpgashells.devices.xilinx.xilinxml507mig._
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import sifive.fpgashells.devices.xilinx.xilinxml507mig._
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import sifive.fpgashells.ip.xilinx.{PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_dvi_clock, ml507_sys_clock, vc707reset}
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import sifive.fpgashells.ip.xilinx.{PowerOnResetFPGAOnly, sdio_spi_bridge, ml507_ddr2_clock, ml507_dvi_clock, ml507_sys_clock, vc707reset}
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//-------------------------------------------------------------------------
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//-------------------------------------------------------------------------
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// ML507Shell
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// ML507Shell
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@ -57,6 +57,10 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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// 100Mhz sysclk
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// 100Mhz sysclk
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val sys_clock = IO(Input(Clock()))
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val sys_clock = IO(Input(Clock()))
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// 200MHz ddrclk
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val ddr_clock_p = IO(Input(Clock()))
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val ddr_clock_n = IO(Input(Clock()))
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// active high async reset
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// active high async reset
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val reset = IO(Input(Bool()))
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val reset = IO(Input(Bool()))
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@ -97,6 +101,12 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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val dvi_clock = Wire(Clock())
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val dvi_clock = Wire(Clock())
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val dvi_reset = Wire(Bool())
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val dvi_reset = Wire(Bool())
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val ddr_clk0 = Wire(Clock())
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val ddr_clk90 = Wire(Clock())
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val ddr_clkdiv0 = Wire(Clock())
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val ddr_clk_locked = Wire(Bool())
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val ddr_reset = Wire(Bool())
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val sd_spi_sck = Wire(Bool())
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val sd_spi_sck = Wire(Bool())
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val sd_spi_cs = Wire(Bool())
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val sd_spi_cs = Wire(Bool())
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val sd_spi_dq_i = Wire(Vec(4, Bool()))
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val sd_spi_dq_i = Wire(Vec(4, Bool()))
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@ -126,9 +136,19 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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ml507_dvi_clock.io.CLKIN_IN := sys_clock
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ml507_dvi_clock.io.CLKIN_IN := sys_clock
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dvi_clock := ml507_dvi_clock.io.CLKFX_OUT
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dvi_clock := ml507_dvi_clock.io.CLKFX_OUT
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// 200 MHz (DDR2 and IDELAY clock)
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val ml507_ddr2_clock = Module(new ml507_ddr2_clock)
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ml507_ddr2_clock.io.CLKIN_P_IN := ddr_clock_p
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ml507_ddr2_clock.io.CLKIN_N_IN := ddr_clock_n
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ddr_clk0 := ml507_ddr2_clock.io.CLK0_OUT
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ddr_clk90 := ml507_ddr2_clock.io.CLK90_OUT
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ddr_clkdiv0 := ml507_ddr2_clock.io.CLKDV_OUT
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ddr_clk_locked := ml507_ddr2_clock.io.LOCKED_OUT
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// Clocks locked?
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// Clocks locked?
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clk_locked := ml507_sys_clock.io.LOCKED_OUT &
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clk_locked := ml507_sys_clock.io.LOCKED_OUT &
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ml507_dvi_clock.io.LOCKED_OUT
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ml507_dvi_clock.io.LOCKED_OUT &
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ddr_clk_locked
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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// System reset
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// System reset
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@ -140,7 +160,8 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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val safe_reset = Module(new vc707reset)
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val safe_reset = Module(new vc707reset)
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safe_reset.io.areset := do_reset
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safe_reset.io.areset := do_reset
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safe_reset.io.clock1 := dut_clock
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safe_reset.io.clock1 := ddr_clk0
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ddr_reset := safe_reset.io.reset1
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safe_reset.io.clock2 := dut_clock
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safe_reset.io.clock2 := dut_clock
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safe_reset.io.clock3 := dvi_clock
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safe_reset.io.clock3 := dvi_clock
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dvi_reset := safe_reset.io.reset3
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dvi_reset := safe_reset.io.reset3
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@ -167,6 +188,13 @@ abstract class ML507Shell(implicit val p: Parameters) extends RawModule {
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def connectDDRMemory(dut: HasMemoryML507ModuleImp): Unit = {
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def connectDDRMemory(dut: HasMemoryML507ModuleImp): Unit = {
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ddr2 <> dut.ddr2
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ddr2 <> dut.ddr2
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dut.ddr_sys.clk0 := ddr_clk0
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dut.ddr_sys.clk90 := ddr_clk90
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dut.ddr_sys.clkdiv0 := ddr_clkdiv0
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dut.ddr_sys.clk_locked := ddr_clk_locked
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dut.ddr_sys.clk_idelay := ddr_clk0
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dut.ddr_sys.reset := ddr_reset
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}
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}
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//-----------------------------------------------------------------------
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//-----------------------------------------------------------------------
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