riscv/fpga-shells
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Add clock generation for the mig

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This commit is contained in:
Klemens Schölhorn
2018-05-10 01:04:52 +02:00
parent 589e9960c0
commit 77694a6741
2 changed files with 42 additions and 3 deletions
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11
src/main/scala/ip/xilinx/Xilinx.scala
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@@ -114,6 +114,17 @@ class ml507_dvi_clock extends BlackBox {
}
}
class ml507_ddr2_clock extends BlackBox {
val io = new Bundle {
val CLKIN_P_IN = Clock(INPUT)
val CLKIN_N_IN = Clock(INPUT)
val CLK0_OUT = Clock(OUTPUT)
val CLK90_OUT = Clock(OUTPUT)
val CLKDV_OUT = Clock(OUTPUT)
val LOCKED_OUT = Bool(OUTPUT)
}
}
//-------------------------------------------------------------------------
// vc707_sys_clock_mmcm
//-------------------------------------------------------------------------