riscv/fpga-shells
1
0
Fork 0
Code Releases Activity

Document address extraction for the mig

Browse Source
This commit is contained in:
Klemens Schölhorn 2018-05-13 19:52:38 +02:00
parent 12cb1c2fa5
commit 700e6b640d
1 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala
View File

@ -44,6 +44,9 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
// Corresponds to MIG interface with 64 bit width and a burst length of 4 // Corresponds to MIG interface with 64 bit width and a burst length of 4
val width = 256 val width = 256
val beatBytes = width/8 // 32 byte (half a cache-line, fragmented) val beatBytes = width/8 // 32 byte (half a cache-line, fragmented)
val address_range = AddressRange.fromSets(c.address).head
require(log2Ceil(address_range.size) == 28, "Max 256MiB DIMMs supported")
val crossing = AsynchronousCrossing(8) val crossing = AsynchronousCrossing(8)
val device = new MemoryDevice val device = new MemoryDevice
@ -90,13 +93,18 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend
// with respect to the size and address. So we can directly forward // with respect to the size and address. So we can directly forward
// the mask, (relative) address and data to the MIG interface. // the mask, (relative) address and data to the MIG interface.
// An AddressSet is always aligned, so we don't need to subtract the
// base address, we can just take the lower bits. The lowest 5 bits
// are used for indexing the 32 byte word of the MIG.
val address = in.a.bits.address(27, 0) & "hFFFFFE0".U
// Save the source, size and type of the requests in a queue so we // Save the source, size and type of the requests in a queue so we
// can synthesize the right responses in fifo order. The length also // can synthesize the right responses in fifo order. The length also
// determines the maximum number of in-flight requests. // determines the maximum number of in-flight requests.
val ack_queue = Module(new Queue(new ResponseQueueIO, 4)) val ack_queue = Module(new Queue(new ResponseQueueIO, 4))
// Pass data directly to the controller // Pass data directly to the controller
controller.io.request_addr := in.a.bits.address(27, 0) & "hFFFFFE0".U controller.io.request_addr := address
controller.io.request_type := !edge.hasData(in.a.bits) controller.io.request_type := !edge.hasData(in.a.bits)
controller.io.request_data := in.a.bits.data controller.io.request_data := in.a.bits.data
// TL uses high to indicate valid data while mig uses low // TL uses high to indicate valid data while mig uses low