From 700e6b640d53c0fc5973d3cd0b0100cda95802f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Klemens=20Sch=C3=B6lhorn?= Date: Sun, 13 May 2018 19:52:38 +0200 Subject: [PATCH] Document address extraction for the mig --- .../devices/xilinx/xilinxml507mig/XilinxML507MIG.scala | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala b/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala index 5c1f016..1943fd1 100644 --- a/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala +++ b/src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala @@ -44,6 +44,9 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend // Corresponds to MIG interface with 64 bit width and a burst length of 4 val width = 256 val beatBytes = width/8 // 32 byte (half a cache-line, fragmented) + + val address_range = AddressRange.fromSets(c.address).head + require(log2Ceil(address_range.size) == 28, "Max 256MiB DIMMs supported") val crossing = AsynchronousCrossing(8) val device = new MemoryDevice @@ -90,13 +93,18 @@ class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extend // with respect to the size and address. So we can directly forward // the mask, (relative) address and data to the MIG interface. + // An AddressSet is always aligned, so we don't need to subtract the + // base address, we can just take the lower bits. The lowest 5 bits + // are used for indexing the 32 byte word of the MIG. + val address = in.a.bits.address(27, 0) & "hFFFFFE0".U + // Save the source, size and type of the requests in a queue so we // can synthesize the right responses in fifo order. The length also // determines the maximum number of in-flight requests. val ack_queue = Module(new Queue(new ResponseQueueIO, 4)) // Pass data directly to the controller - controller.io.request_addr := in.a.bits.address(27, 0) & "hFFFFFE0".U + controller.io.request_addr := address controller.io.request_type := !edge.hasData(in.a.bits) controller.io.request_data := in.a.bits.data // TL uses high to indicate valid data while mig uses low