Move XilinxML507MIGToTL and MIG into a separate clock domain

src/main/scala/devices/xilinx/xilinxml507mig/XilinxML507MIG.scala

@@ -6,6 +6,7 @@ import Chisel._
 import chisel3.core.{Input, Output}
 import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.subsystem.{AsynchronousCrossing, HasCrossing}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util._
 
@@ -33,10 +34,11 @@ class MemoryController extends BlackBox {
     override def desiredName: String = "memory_controller"
 }
 
-class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extends LazyModule {
+class XilinxML507MIGToTL(c: XilinxML507MIGParams)(implicit p: Parameters) extends LazyModule with HasCrossing {
     // Corresponds to MIG interface with 64 bit width and a burst length of 4
     val width = 256
     val beatBytes = width/8 // 32 byte (half a cache-line, fragmented)
+    val crossing = AsynchronousCrossing(8)
 
     val device = new MemoryDevice
     val node = TLManagerNode(
@@ -126,7 +128,7 @@ class XilinxML507MIG(c : XilinxML507MIGParams)(implicit p: Parameters) extends L
     val island = LazyModule(new XilinxML507MIGToTL(c))
 
     val node: TLInwardNode =
-        island.node := fragmenter.node
+        island.node := island.crossTLIn := fragmenter.node
 
     lazy val module = new LazyModuleImp(this) {
         val io = IO(new Bundle {
@@ -136,5 +138,10 @@ class XilinxML507MIG(c : XilinxML507MIGParams)(implicit p: Parameters) extends L
 
         io.port_sys <> island.module.io.port_sys
         io.port_ddr2 <> island.module.io.port_ddr2
+
+        // The MIGToTL module lives in a separate clock domain together with
+        // the MIG, which is why it is called "island".
+        island.module.clock := io.port_sys.clk0
+        island.module.reset := io.port_sys.reset
     }
 }