library ieee;

use ieee.std_logic_1164.all;

entity CPLD2 is
    port (
        func: in std_logic_vector(3 downto 0);
        accu: in std_logic_vector(15 downto 8);
        ram: in std_logic_vector(15 downto 8);
        carry_in: in std_logic;
        result: out std_logic_vector(15 downto 8)
    );
end CPLD2;

architecture rtl of CPLD2 is
begin

    alu: entity work.alu generic map (
        WIDTH => 8,
        FIRST => false
    ) port map (
        func => func,
        accu => accu,
        ram => ram,
        carry_in => carry_in,
        result => result,
        carry_out => open
    );

end rtl;