Create 6 bit version for two XC9536XL CPLDs

Tested with two BitConnector breakout boards [1].

[1]: https://github.com/1ux/BitConnector

boards/alu/alu-cache.lib

@@ -1,14 +1,13 @@
-EESchema-LIBRARY Version 2.3
+EESchema-LIBRARY Version 2.4
 #encoding utf-8
 #
-# AP1117
+# alu-rescue:AP1117D33
 #
-DEF AP1117 U 0 30 Y Y 1 F N
+DEF alu-rescue:AP1117D33 U 0 30 Y Y 1 F N
 F0 "U" 100 -250 50 H V C CNN
-F1 "AP1117" 0 250 50 H V C CNN
+F1 "alu-rescue:AP1117D33" 0 250 50 H V C CNN
 F2 "" 0 0 50 H V C CNN
 F3 "" 0 0 50 H V C CNN
-ALIAS AP1117D15 AP1117D18 AP1117D25 AP1117D33 AP1117D50 AP1117E15 AP1117E18 AP1117E25 AP1117E33 AP1117E50 AP1117K15 AP1117K18 AP1117K25 AP1117K33 AP1117K50 AP1117T15 AP1117T18 AP1117T25 AP1117T33 AP1117T50 AP1117Y15 AP1117Y18 AP1117Y25 AP1117Y33 AP1117Y50
 $FPLIST
  SOT223
  SOT89-3
@@ -24,11 +23,11 @@ X VI 3 -300 0 100 R 50 50 1 1 W
 ENDDRAW
 ENDDEF
 #
-# Conn_01x02
+# alu-rescue:Conn_01x02
 #
-DEF Conn_01x02 J 0 40 Y N 1 F N
+DEF alu-rescue:Conn_01x02 J 0 40 Y N 1 F N
 F0 "J" 0 100 50 H V C CNN
-F1 "Conn_01x02" 0 -200 50 H V C CNN
+F1 "alu-rescue:Conn_01x02" 0 -200 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
@@ -48,11 +47,11 @@ X Pin_2 2 -200 -100 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Conn_01x04
+# alu-rescue:Conn_01x04
 #
-DEF Conn_01x04 J 0 40 Y N 1 F N
+DEF alu-rescue:Conn_01x04 J 0 40 Y N 1 F N
 F0 "J" 0 200 50 H V C CNN
-F1 "Conn_01x04" 0 -300 50 H V C CNN
+F1 "alu-rescue:Conn_01x04" 0 -300 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
@@ -76,11 +75,11 @@ X Pin_4 4 -200 -200 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# Conn_01x16
+# alu-rescue:Conn_01x16
 #
-DEF Conn_01x16 J 0 40 Y N 1 F N
+DEF alu-rescue:Conn_01x16 J 0 40 Y N 1 F N
 F0 "J" 0 800 50 H V C CNN
-F1 "Conn_01x16" 0 -900 50 H V C CNN
+F1 "alu-rescue:Conn_01x16" 0 -900 50 H V C CNN
 F2 "" 0 0 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 $FPLIST
@@ -110,6 +109,13 @@ S -50 605 0 595 1 1 6 N
 S -50 705 0 695 1 1 6 N
 S -50 750 50 -850 1 1 10 f
 X Pin_1 1 -200 700 150 R 50 50 1 1 P
+X Pin_10 10 -200 -200 150 R 50 50 1 1 P
+X Pin_11 11 -200 -300 150 R 50 50 1 1 P
+X Pin_12 12 -200 -400 150 R 50 50 1 1 P
+X Pin_13 13 -200 -500 150 R 50 50 1 1 P
+X Pin_14 14 -200 -600 150 R 50 50 1 1 P
+X Pin_15 15 -200 -700 150 R 50 50 1 1 P
+X Pin_16 16 -200 -800 150 R 50 50 1 1 P
 X Pin_2 2 -200 600 150 R 50 50 1 1 P
 X Pin_3 3 -200 500 150 R 50 50 1 1 P
 X Pin_4 4 -200 400 150 R 50 50 1 1 P
@@ -118,109 +124,102 @@ X Pin_6 6 -200 200 150 R 50 50 1 1 P
 X Pin_7 7 -200 100 150 R 50 50 1 1 P
 X Pin_8 8 -200 0 150 R 50 50 1 1 P
 X Pin_9 9 -200 -100 150 R 50 50 1 1 P
-X Pin_10 10 -200 -200 150 R 50 50 1 1 P
-X Pin_11 11 -200 -300 150 R 50 50 1 1 P
-X Pin_12 12 -200 -400 150 R 50 50 1 1 P
-X Pin_13 13 -200 -500 150 R 50 50 1 1 P
-X Pin_14 14 -200 -600 150 R 50 50 1 1 P
-X Pin_15 15 -200 -700 150 R 50 50 1 1 P
-X Pin_16 16 -200 -800 150 R 50 50 1 1 P
 ENDDRAW
 ENDDEF
 #
-# GND
+# power:GND
 #
-DEF GND #PWR 0 0 Y Y 1 F P
+DEF power:GND #PWR 0 0 Y Y 1 F P
 F0 "#PWR" 0 -250 50 H I C CNN
-F1 "GND" 0 -150 50 H V C CNN
+F1 "power:GND" 0 -150 50 H V C CNN
-F2 "" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H I C CNN
 DRAW
-P 6 0 1 0  0 0  0 -50  50 -50  0 -100  -50 -50  0 -50 N
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
 X GND 1 0 0 0 D 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
-# PWR_FLAG
+# power:PWR_FLAG
 #
-DEF PWR_FLAG #FLG 0 0 N N 1 F P
+DEF power:PWR_FLAG #FLG 0 0 N N 1 F P
-F0 "#FLG" 0 95 50 H I C CNN
+F0 "#FLG" 0 75 50 H I C CNN
-F1 "PWR_FLAG" 0 180 50 H V C CNN
+F1 "power:PWR_FLAG" 0 150 50 H V C CNN
-F2 "" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H I C CNN
 DRAW
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
 X pwr 1 0 0 0 U 50 50 0 0 w
-P 6 0 1 0  0 0  0 50  -75 100  0 150  75 100  0 50 N
 ENDDRAW
 ENDDEF
 #
-# VCC
+# power:VCC
 #
-DEF VCC #PWR 0 0 Y Y 1 F P
+DEF power:VCC #PWR 0 0 Y Y 1 F P
 F0 "#PWR" 0 -150 50 H I C CNN
-F1 "VCC" 0 150 50 H V C CNN
+F1 "power:VCC" 0 150 50 H V C CNN
-F2 "" 0 0 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
-F3 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H I C CNN
 DRAW
 C 0 75 25 0 1 0 N
-P 2 0 1 0  0 0  0 50 N
+P 2 0 1 0 0 0 0 50 N
 X VCC 1 0 0 0 U 50 50 1 1 W N
 ENDDRAW
 ENDDEF
 #
-# XC9572XL-VQ44
+# xilinx:XC9572XL-VQ44
 #
-DEF XC9572XL-VQ44 U 0 40 Y Y 1 F N
+DEF xilinx:XC9572XL-VQ44 U 0 40 Y Y 1 F N
 F0 "U" 1254 -1370 39 H V C CNN
-F1 "XC9572XL-VQ44" -1139 -1347 39 H V C CNN
+F1 "xilinx:XC9572XL-VQ44" -1139 -1347 39 H V C CNN
 F2 "" -200 -150 60 H I C CNN
 F3 "" -200 -150 60 H I C CNN
 DRAW
 S -1300 1300 1300 -1300 0 1 0 N
 X I/O/GCK3 1 -750 -1500 200 U 50 50 1 1 B
+X TMS 10 600 -1500 200 U 50 50 1 1 B
+X TCK 11 750 -1500 200 U 50 50 1 1 B
+X ~ 12 1500 -750 200 L 50 50 1 1 B
+X ~ 13 1500 -600 200 L 50 50 1 1 B
+X ~ 14 1500 -450 200 L 50 50 1 1 B
+X VCC_INT 15 1500 -300 200 L 50 50 1 1 W
+X ~ 16 1500 -150 200 L 50 50 1 1 B
+X GND 17 1500 0 200 L 50 50 1 1 W
+X ~ 18 1500 150 200 L 50 50 1 1 B
+X ~ 19 1500 300 200 L 50 50 1 1 B
 X ~ 2 -600 -1500 200 U 50 50 1 1 B
+X ~ 20 1500 450 200 L 50 50 1 1 B
+X ~ 21 1500 600 200 L 50 50 1 1 B
+X ~ 22 1500 750 200 L 50 50 1 1 B
+X ~ 23 750 1500 200 D 50 50 1 1 B
+X TDO 24 600 1500 200 D 50 50 1 1 B
+X GND 25 450 1500 200 D 50 50 1 1 W
+X VCC_IO 26 300 1500 200 D 50 50 1 1 W
+X ~ 27 150 1500 200 D 50 50 1 1 B
+X ~ 28 0 1500 200 D 50 50 1 1 B
+X ~ 29 -150 1500 200 D 50 50 1 1 B
 X ~ 3 -450 -1500 200 U 50 50 1 1 B
+X ~ 30 -300 1500 200 D 50 50 1 1 B
+X ~ 31 -450 1500 200 D 50 50 1 1 B
+X ~ 32 -600 1500 200 D 50 50 1 1 B
+X I/O/GSR 33 -750 1500 200 D 50 50 1 1 B
+X I/O/GTS2 34 -1500 750 200 R 50 50 1 1 B
+X VCC_INT 35 -1500 600 200 R 50 50 1 1 W
+X I/O/GTS1 36 -1500 450 200 R 50 50 1 1 B
+X ~ 37 -1500 300 200 R 50 50 1 1 B
+X ~ 38 -1500 150 200 R 50 50 1 1 B
+X ~ 39 -1500 0 200 R 50 50 1 1 B
 X GND 4 -300 -1500 200 U 50 50 1 1 W
+X ~ 40 -1500 -150 200 R 50 50 1 1 B
+X ~ 41 -1500 -300 200 R 50 50 1 1 B
+X ~ 42 -1500 -450 200 R 50 50 1 1 B
+X I/O/GCK1 43 -1500 -600 200 R 50 50 1 1 B
+X I/O/GCK2 44 -1500 -750 200 R 50 50 1 1 B
 X ~ 5 -150 -1500 200 U 50 50 1 1 B
 X ~ 6 0 -1500 200 U 50 50 1 1 B
 X ~ 7 150 -1500 200 U 50 50 1 1 B
 X ~ 8 300 -1500 200 U 50 50 1 1 B
 X TDI 9 450 -1500 200 U 50 50 1 1 B
-X TMS 10 600 -1500 200 U 50 50 1 1 B
-X ~ 20 1500 450 200 L 50 50 1 1 B
-X ~ 30 -300 1500 200 D 50 50 1 1 B
-X ~ 40 -1500 -150 200 R 50 50 1 1 B
-X TCK 11 750 -1500 200 U 50 50 1 1 B
-X ~ 21 1500 600 200 L 50 50 1 1 B
-X ~ 31 -450 1500 200 D 50 50 1 1 B
-X ~ 41 -1500 -300 200 R 50 50 1 1 B
-X ~ 12 1500 -750 200 L 50 50 1 1 B
-X ~ 22 1500 750 200 L 50 50 1 1 B
-X ~ 32 -600 1500 200 D 50 50 1 1 B
-X ~ 42 -1500 -450 200 R 50 50 1 1 B
-X ~ 13 1500 -600 200 L 50 50 1 1 B
-X ~ 23 750 1500 200 D 50 50 1 1 B
-X I/O/GSR 33 -750 1500 200 D 50 50 1 1 B
-X I/O/GCK1 43 -1500 -600 200 R 50 50 1 1 B
-X ~ 14 1500 -450 200 L 50 50 1 1 B
-X TDO 24 600 1500 200 D 50 50 1 1 B
-X I/O/GTS2 34 -1500 750 200 R 50 50 1 1 B
-X I/O/GCK2 44 -1500 -750 200 R 50 50 1 1 B
-X VCC_INT 15 1500 -300 200 L 50 50 1 1 W
-X GND 25 450 1500 200 D 50 50 1 1 W
-X VCC_INT 35 -1500 600 200 R 50 50 1 1 W
-X ~ 16 1500 -150 200 L 50 50 1 1 B
-X VCC_IO 26 300 1500 200 D 50 50 1 1 W
-X I/O/GTS1 36 -1500 450 200 R 50 50 1 1 B
-X GND 17 1500 0 200 L 50 50 1 1 W
-X ~ 27 150 1500 200 D 50 50 1 1 B
-X ~ 37 -1500 300 200 R 50 50 1 1 B
-X ~ 18 1500 150 200 L 50 50 1 1 B
-X ~ 28 0 1500 200 D 50 50 1 1 B
-X ~ 38 -1500 150 200 R 50 50 1 1 B
-X ~ 19 1500 300 200 L 50 50 1 1 B
-X ~ 29 -150 1500 200 D 50 50 1 1 B
-X ~ 39 -1500 0 200 R 50 50 1 1 B
 ENDDRAW
 ENDDEF
 #

boards/alu/alu.pro

@@ -1,4 +1,4 @@
-update=2018-05-19T16:41:18 CEST
+update=Do 27 Sep 2018 15:26:18 CEST
 version=1
 last_client=kicad
 [pcbnew]
@@ -28,36 +28,3 @@ version=1
 [eeschema]
 version=1
 LibDir=
-[eeschema/libraries]
-LibName1=power
-LibName2=device
-LibName3=switches
-LibName4=relays
-LibName5=motors
-LibName6=transistors
-LibName7=conn
-LibName8=linear
-LibName9=regul
-LibName10=74xx
-LibName11=cmos4000
-LibName12=adc-dac
-LibName13=memory
-LibName14=xilinx
-LibName15=microcontrollers
-LibName16=dsp
-LibName17=microchip
-LibName18=analog_switches
-LibName19=motorola
-LibName20=texas
-LibName21=intel
-LibName22=audio
-LibName23=interface
-LibName24=digital-audio
-LibName25=philips
-LibName26=display
-LibName27=cypress
-LibName28=siliconi
-LibName29=opto
-LibName30=atmel
-LibName31=contrib
-LibName32=valves

boards/alu/alu.sch

@@ -1,37 +1,6 @@
-EESchema Schematic File Version 2
+EESchema Schematic File Version 4
-LIBS:power
-LIBS:device
-LIBS:switches
-LIBS:relays
-LIBS:transistors
-LIBS:conn
-LIBS:linear
-LIBS:regul
-LIBS:74xx
-LIBS:cmos4000
-LIBS:adc-dac
-LIBS:memory
-LIBS:xilinx
-LIBS:microcontrollers
-LIBS:dsp
-LIBS:microchip
-LIBS:analog_switches
-LIBS:motorola
-LIBS:texas
-LIBS:intel
-LIBS:audio
-LIBS:interface
-LIBS:digital-audio
-LIBS:philips
-LIBS:display
-LIBS:cypress
-LIBS:siliconi
-LIBS:opto
-LIBS:atmel
-LIBS:contrib
-LIBS:valves
 LIBS:alu-cache
-EELAYER 25 0
+EELAYER 26 0
 EELAYER END
 $Descr A3 16535 11693
 encoding utf-8
@@ -46,7 +15,7 @@ Comment3 ""
 Comment4 ""
 $EndDescr
 $Comp
-L Conn_01x16 J4
+L alu-rescue:Conn_01x16 J4
 U 1 1 5AEB13AD
 P 12050 4800
 F 0 "J4" H 12050 5600 50  0000 C CNN
@@ -57,7 +26,7 @@ F 3 "" H 12050 4800 50  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L Conn_01x16 J3
+L alu-rescue:Conn_01x16 J3
 U 1 1 5AEB13CF
 P 2600 6900
 F 0 "J3" H 2600 7700 50  0000 C CNN
@@ -68,7 +37,7 @@ F 3 "" H 2600 6900 50  0001 C CNN
 	-1   0    0    1   
 $EndComp
 $Comp
-L Conn_01x16 J5
+L alu-rescue:Conn_01x16 J5
 U 1 1 5AEB143D
 P 2600 4300
 F 0 "J5" H 2600 5100 50  0000 C CNN
@@ -79,7 +48,7 @@ F 3 "" H 2600 4300 50  0001 C CNN
 	-1   0    0    1   
 $EndComp
 $Comp
-L Conn_01x02 J2
+L alu-rescue:Conn_01x02 J2
 U 1 1 5AEB171D
 P 3300 2400
 F 0 "J2" H 3300 2500 50  0000 C CNN
@@ -90,7 +59,7 @@ F 3 "" H 3300 2400 50  0001 C CNN
 	-1   0    0    1   
 $EndComp
 $Comp
-L Conn_01x04 J1
+L alu-rescue:Conn_01x04 J1
 U 1 1 5AEB1744
 P 8350 9350
 F 0 "J1" H 8350 9550 50  0000 C CNN
@@ -101,7 +70,7 @@ F 3 "" H 8350 9350 50  0001 C CNN
 	0    1    1    0   
 $EndComp
 $Comp
-L GND #PWR01
+L power:GND #PWR01
 U 1 1 5AEB5098
 P 4500 2300
 F 0 "#PWR01" H 4500 2050 50  0001 C CNN
@@ -112,7 +81,7 @@ F 3 "" H 4500 2300 50  0001 C CNN
 	-1   0    0    1   
 $EndComp
 $Comp
-L VCC #PWR02
+L power:VCC #PWR02
 U 1 1 5AEB50BA
 P 4800 2600
 F 0 "#PWR02" H 4800 2450 50  0001 C CNN
@@ -133,7 +102,7 @@ NoConn ~ 9350 4050
 NoConn ~ 9200 6350
 NoConn ~ 8450 5600
 $Comp
-L XC9572XL-VQ44 U1
+L xilinx:XC9572XL-VQ44 U1
 U 1 1 5B07240B
 P 7850 3300
 F 0 "U1" H 9104 1930 39  0000 C CNN
@@ -144,7 +113,7 @@ F 3 "" H 7650 3150 60  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L XC9572XL-VQ44 U2
+L xilinx:XC9572XL-VQ44 U2
 U 1 1 5B07250D
 P 7700 7100
 F 0 "U2" H 8954 5730 39  0000 C CNN
@@ -155,7 +124,7 @@ F 3 "" H 7500 6950 60  0001 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L AP1117D33 U3
+L alu-rescue:AP1117D33 U3
 U 1 1 5B2BB004
 P 4500 2600
 F 0 "U3" H 4600 2350 50  0000 C CNN
@@ -166,7 +135,7 @@ F 3 "" H 4500 2600 50  0000 C CNN
 	1    0    0    1   
 $EndComp
 $Comp
-L VCC #PWR03
+L power:VCC #PWR03
 U 1 1 5B2BB87A
 P 8150 1800
 F 0 "#PWR03" H 8150 1650 50  0001 C CNN
@@ -177,7 +146,7 @@ F 3 "" H 8150 1800 50  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L VCC #PWR04
+L power:VCC #PWR04
 U 1 1 5B2BB938
 P 6350 2700
 F 0 "#PWR04" H 6350 2550 50  0001 C CNN
@@ -188,7 +157,7 @@ F 3 "" H 6350 2700 50  0000 C CNN
 	0    -1   -1   0   
 $EndComp
 $Comp
-L VCC #PWR05
+L power:VCC #PWR05
 U 1 1 5B2BBA36
 P 6200 6500
 F 0 "#PWR05" H 6200 6350 50  0001 C CNN
@@ -199,7 +168,7 @@ F 3 "" H 6200 6500 50  0000 C CNN
 	0    -1   -1   0   
 $EndComp
 $Comp
-L VCC #PWR06
+L power:VCC #PWR06
 U 1 1 5B2BBA6C
 P 8000 5600
 F 0 "#PWR06" H 8000 5450 50  0001 C CNN
@@ -210,7 +179,7 @@ F 3 "" H 8000 5600 50  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L PWR_FLAG #FLG07
+L power:PWR_FLAG #FLG07
 U 1 1 5B2BBD33
 P 3600 2450
 F 0 "#FLG07" H 3600 2545 50  0001 C CNN
@@ -221,7 +190,7 @@ F 3 "" H 3600 2450 50  0000 C CNN
 	-1   0    0    1   
 $EndComp
 $Comp
-L GND #PWR08
+L power:GND #PWR08
 U 1 1 5B2BBFFE
 P 8300 1800
 F 0 "#PWR08" H 8300 1550 50  0001 C CNN
@@ -232,7 +201,7 @@ F 3 "" H 8300 1800 50  0000 C CNN
 	-1   0    0    1   
 $EndComp
 $Comp
-L GND #PWR09
+L power:GND #PWR09
 U 1 1 5B2BC054
 P 8150 5600
 F 0 "#PWR09" H 8150 5350 50  0001 C CNN
@@ -243,7 +212,7 @@ F 3 "" H 8150 5600 50  0000 C CNN
 	-1   0    0    1   
 $EndComp
 $Comp
-L PWR_FLAG #FLG010
+L power:PWR_FLAG #FLG010
 U 1 1 5B2BC373
 P 3600 2250
 F 0 "#FLG010" H 3600 2345 50  0001 C CNN
@@ -254,7 +223,7 @@ F 3 "" H 3600 2250 50  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR011
+L power:GND #PWR011
 U 1 1 5B2BCDC3
 P 9200 7100
 F 0 "#PWR011" H 9200 6850 50  0001 C CNN
@@ -265,7 +234,7 @@ F 3 "" H 9200 7100 50  0000 C CNN
 	0    -1   -1   0   
 $EndComp
 $Comp
-L GND #PWR012
+L power:GND #PWR012
 U 1 1 5B2BCEE1
 P 9350 3300
 F 0 "#PWR012" H 9350 3050 50  0001 C CNN
@@ -276,7 +245,7 @@ F 3 "" H 9350 3300 50  0000 C CNN
 	0    -1   -1   0   
 $EndComp
 $Comp
-L GND #PWR013
+L power:GND #PWR013
 U 1 1 5B2BD11F
 P 7400 8600
 F 0 "#PWR013" H 7400 8350 50  0001 C CNN
@@ -287,7 +256,7 @@ F 3 "" H 7400 8600 50  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L GND #PWR014
+L power:GND #PWR014
 U 1 1 5B2BD205
 P 7550 4800
 F 0 "#PWR014" H 7550 4550 50  0001 C CNN
@@ -298,7 +267,7 @@ F 3 "" H 7550 4800 50  0000 C CNN
 	1    0    0    -1  
 $EndComp
 $Comp
-L VCC #PWR015
+L power:VCC #PWR015
 U 1 1 5B2BD49C
 P 9350 3600
 F 0 "#PWR015" H 9350 3450 50  0001 C CNN
@@ -309,7 +278,7 @@ F 3 "" H 9350 3600 50  0000 C CNN
 	0    1    1    0   
 $EndComp
 $Comp
-L VCC #PWR016
+L power:VCC #PWR016
 U 1 1 5B2BD61A
 P 9200 7400
 F 0 "#PWR016" H 9200 7250 50  0001 C CNN
@@ -320,7 +289,7 @@ F 3 "" H 9200 7400 50  0000 C CNN
 	0    1    1    0   
 $EndComp
 $Comp
-L Conn_01x04 J6
+L alu-rescue:Conn_01x04 J6
 U 1 1 5B2BF128
 P 5100 6100
 F 0 "J6" H 5100 6300 50  0000 C CNN
@@ -331,7 +300,7 @@ F 3 "" H 5100 6100 50  0001 C CNN
 	-1   0    0    -1  
 $EndComp
 Wire Wire Line
-	3500 2300 4500 2300
+	3500 2300 3600 2300
 Wire Wire Line
 	8300 4800 8300 5600
 Wire Wire Line
@@ -339,13 +308,13 @@ Wire Wire Line
 Wire Wire Line
 	8250 9050 8250 9150
 Wire Wire Line
-	8250 9050 10100 9050
+	8250 9050 8300 9050
 Wire Wire Line
 	8300 8600 8300 9050
 Wire Wire Line
 	8350 9150 8350 9100
 Wire Wire Line
-	8350 9100 10150 9100
+	8350 9100 8450 9100
 Wire Wire Line
 	8450 9100 8450 8600
 Wire Wire Line
@@ -546,10 +515,6 @@ Wire Wire Line
 	4175 3300 6350 3300
 Wire Wire Line
 	4300 6200 4300 3450
-Wire Wire Line
-	4300 3450 6350 3450
-Wire Wire Line
-	6275 3450 6275 3450
 Wire Wire Line
 	4425 3600 6350 3600
 Wire Wire Line
@@ -693,7 +658,7 @@ Wire Wire Line
 Wire Wire Line
 	8150 5200 8150 4800
 Wire Wire Line
-	3500 2400 4200 2400
+	3500 2400 3600 2400
 Wire Wire Line
 	4200 2400 4200 2600
 Wire Wire Line
@@ -719,7 +684,7 @@ Wire Wire Line
 Wire Wire Line
 	5300 6300 5850 6300
 Wire Wire Line
-	5850 4950 5850 7400
+	5850 4950 5850 6300
 Wire Wire Line
 	5850 4950 7250 4950
 Wire Wire Line
@@ -727,7 +692,7 @@ Wire Wire Line
 Wire Wire Line
 	5300 6200 5800 6200
 Wire Wire Line
-	5800 4850 5800 7550
+	5800 4850 5800 6200
 Wire Wire Line
 	5800 4850 7100 4850
 Wire Wire Line
@@ -735,13 +700,13 @@ Wire Wire Line
 Wire Wire Line
 	5300 6100 5750 6100
 Wire Wire Line
-	5750 4050 5750 7700
+	5750 4050 5750 6100
 Wire Wire Line
 	5750 4050 6350 4050
 Wire Wire Line
 	5300 6000 5700 6000
 Wire Wire Line
-	5700 3900 5700 7850
+	5700 3900 5700 6000
 Wire Wire Line
 	5700 3900 6350 3900
 Wire Wire Line
@@ -756,4 +721,22 @@ Connection ~ 5750 6100
 Wire Wire Line
 	5700 7850 6200 7850
 Connection ~ 5700 6000
+Wire Wire Line
+	8450 9100 10150 9100
+Wire Wire Line
+	8300 9050 10100 9050
+Wire Wire Line
+	3600 2300 4500 2300
+Wire Wire Line
+	3600 2400 4200 2400
+Wire Wire Line
+	5850 6300 5850 7400
+Wire Wire Line
+	5800 6200 5800 7550
+Wire Wire Line
+	5750 6100 5750 7700
+Wire Wire Line
+	5700 6000 5700 7850
+Wire Wire Line
+	4300 3450 6350 3450
 $EndSCHEMATC

boards/alu/sym-lib-table

@@ -0,0 +1,4 @@
+(sym_lib_table
+  (lib (name alu-rescue)(type Legacy)(uri ${KIPRJMOD}/alu-rescue.lib)(options "")(descr ""))
+  (lib (name xilinx)(type Legacy)(uri ${KIPRJMOD}/xilinx.lib)(options "")(descr ""))
+)

doc/ALU-Pins.md

@@ -0,0 +1,44 @@
+# ALU Pins
+
+## CPLD1
+
+> Das *Obere*.
+
+| Nr. | ACC  | RAM  | Y (Result) |
+|:---:|:----:|:----:|:----:|
+| 0   | 27   | 39   | 22   |
+| 1   | 28   | 40   | 21   |
+| 2   | 29   | 41   | 20   |
+| 3   | 30   | 42   | 19   |
+| 4   | 31   | 5    | 18   |
+| 5   | 32   | 6    | 16   |
+| 6   | 37   | 7    | 14   |
+| 7   | 38   | 8    | 13   |
+
+**CO: Pin 3** (Carry Out)
+
+## CPLD2
+
+> Das *Untere*.
+
+| Nr. | ACC  | RAM  | Y (Result) |
+|:---:|:----:|:----:|:----:|
+| 8   | 27   | 39   | 21   |
+| 9   | 28   | 40   | 20   |
+| A   | 29   | 2    | 19   |
+| B   | 30   | 3    | 18   |
+| C   | 31   | 5    | 16   |
+| D   | 32   | 6    | 14   |
+| E   | 37   | 7    | 13   |
+| F   | 38   | 8    | 12   |
+
+**CI: Pin 33** (Carry In)
+
+## Funktion Pins
+
+| F | CPLD1 | CPLD2 |
+|:-:|:-----:|:-----:|
+| 0 | 43    | 44    |
+| 1 | 44    | 43    |
+| 2 | 1     | 42    |
+| 3 | 2     | 41    |

firmware/alu/.gitignore

@@ -87,6 +87,7 @@ xilinxsim.ini
 
 # cpld
 /main_html/
+*_html/
 *.gyd
 *.jed
 *.mfd
@@ -96,4 +97,6 @@ xilinxsim.ini
 *.vm6
 *.xml
 *.err
+*.tim
+*.tspec
 

firmware/alu/CPLD1.ucf

@@ -0,0 +1,27 @@
+NET "func(0)"       LOC = "27";
+NET "func(1)"       LOC = "28";
+NET "func(2)"       LOC = "29";
+NET "func(3)"       LOC = "30";
+
+NET "accu(0)"       LOC = "31";
+NET "accu(1)"       LOC = "32";
+NET "accu(2)"       LOC = "34";
+NET "accu(3)"       LOC = "36";
+NET "accu(4)"       LOC = "37";
+NET "accu(5)"       LOC = "38";
+
+NET "ram(0)"        LOC = "39";
+NET "ram(1)"        LOC = "40";
+NET "ram(2)"        LOC = "41";
+NET "ram(3)"        LOC = "42";
+NET "ram(4)"        LOC = "43";
+NET "ram(5)"        LOC = "44";
+
+NET "result(0)"     LOC = "23";
+NET "result(1)"     LOC = "22";
+NET "result(2)"     LOC = "21";
+NET "result(3)"     LOC = "20";
+NET "result(4)"     LOC = "19";
+NET "result(5)"     LOC = "18";
+
+NET "carry_out"     LOC = "16";

firmware/alu/CPLD1.vhd

@@ -0,0 +1,30 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+
+entity CPLD1 is
+    port (
+        func: in std_logic_vector(3 downto 0);
+        accu: in std_logic_vector(5 downto 0);
+        ram: in std_logic_vector(5 downto 0);
+        result: out std_logic_vector(5 downto 0);
+        carry_out: out std_logic
+    );
+end CPLD1;
+
+architecture rtl of CPLD1 is
+begin
+
+    alu: entity work.alu generic map (
+        WIDTH => 6,
+        FIRST => true
+    ) port map (
+        func => func,
+        accu => accu,
+        ram => ram,
+        carry_in => '0',
+        result => result,
+        carry_out => carry_out
+    );
+
+end rtl;

firmware/alu/CPLD2.ucf

@@ -0,0 +1,27 @@
+NET "func(0)"       LOC = "27";
+NET "func(1)"       LOC = "28";
+NET "func(2)"       LOC = "29";
+NET "func(3)"       LOC = "30";
+
+NET "accu(6)"       LOC = "31";
+NET "accu(7)"       LOC = "32";
+NET "accu(8)"       LOC = "34";
+NET "accu(9)"       LOC = "36";
+NET "accu(10)"      LOC = "37";
+NET "accu(11)"      LOC = "38";
+
+NET "ram(6)"        LOC = "39";
+NET "ram(7)"        LOC = "40";
+NET "ram(8)"        LOC = "41";
+NET "ram(9)"        LOC = "42";
+NET "ram(10)"       LOC = "43";
+NET "ram(11)"       LOC = "44";
+
+NET "result(6)"     LOC = "23";
+NET "result(7)"     LOC = "22";
+NET "result(8)"     LOC = "21";
+NET "result(9)"     LOC = "20";
+NET "result(10)"    LOC = "19";
+NET "result(11)"    LOC = "18";
+
+NET "carry_in"      LOC = "16";

firmware/alu/CPLD2.vhd

@@ -0,0 +1,30 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+
+entity CPLD2 is
+    port (
+        func: in std_logic_vector(3 downto 0);
+        accu: in std_logic_vector(11 downto 6);
+        ram: in std_logic_vector(11 downto 6);
+        carry_in: in std_logic;
+        result: out std_logic_vector(11 downto 6)
+    );
+end CPLD2;
+
+architecture rtl of CPLD2 is
+begin
+
+    alu: entity work.alu generic map (
+        WIDTH => 6,
+        FIRST => false
+    ) port map (
+        func => func,
+        accu => accu,
+        ram => ram,
+        carry_in => carry_in,
+        result => result,
+        carry_out => open
+    );
+
+end rtl;

firmware/alu/alu.vhd

@@ -3,7 +3,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.ALL;
 
-entity main is
+entity alu is
     generic (
         WIDTH: integer := 8;
         FIRST: boolean := true
@@ -16,9 +16,9 @@ entity main is
         result: out std_logic_vector(WIDTH-1 downto 0);
         carry_out: out std_logic
     );
-end main;
+end alu;
 
-architecture rtl of main is
+architecture rtl of alu is
     signal x: std_logic_vector(WIDTH-1 downto 0);
     signal y: std_logic_vector(WIDTH-1 downto 0);
     signal cin: std_logic;

firmware/alu/alu.xise

@@ -15,10 +15,6 @@
   <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
 
   <files>
-    <file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
-    </file>
     <file xil_pn:name="adder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
@@ -29,7 +25,25 @@
     </file>
     <file xil_pn:name="tests/control_logic.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+    </file>
+    <file xil_pn:name="CPLD1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="CPLD2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+    </file>
+    <file xil_pn:name="alu.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="CPLD2.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="CPLD1.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
 
@@ -39,7 +53,7 @@
     <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Autosignature Generation" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -47,8 +61,10 @@
     <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
     <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Collapsing Input Limit (2-36)" xil_pn:value="36" xil_pn:valueState="default"/>
-    <property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="25" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Input Limit (2-54)" xil_pn:value="54" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (1-90)" xil_pn:value="90" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -58,9 +74,9 @@
     <property xil_pn:name="Create Programmable GND Pins on Unused I/O" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc9572" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="XC9500 CPLDs" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-7" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-10" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable FASTConnect/UIM optimization" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -84,11 +100,12 @@
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Pin Termination" xil_pn:value="Keeper" xil_pn:valueState="default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Balance" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|CPLD2|rtl" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="tests/control_logic.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="CPLD2.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/control_logic" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/CPLD2" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -105,8 +122,8 @@
     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Local Macrocell Feedback" xil_pn:value="On" xil_pn:valueState="default"/>
+    <property xil_pn:name="Local Macrocell Feedback" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
     <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -134,16 +151,16 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="CPLD2" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="PC44" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="VQ44" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Pin Feedback" xil_pn:value="On" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pin Feedback" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="control_logic_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="CPLD2_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="control_logic_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="CPLD2_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="control_logic_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="CPLD2_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="control_logic_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="CPLD2_translate.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
     <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -179,9 +196,10 @@
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.control_logic" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-7" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target UCF File Name" xil_pn:value="CPLD1.ucf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
@@ -219,7 +237,7 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|control_logic|test" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="alu" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
@@ -233,7 +251,10 @@
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
 
-  <bindings/>
+  <bindings>
+    <binding xil_pn:location="/CPLD2" xil_pn:name="CPLD2.ucf"/>
+    <binding xil_pn:location="/CPLD1" xil_pn:name="CPLD1.ucf"/>
+  </bindings>
 
   <libraries/>