Add schematic for generating multiple enabled clocks

doc/clock_generation.sch

@@ -0,0 +1,188 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4027 U?
+U 1 1 5AFDD0CA
+P 4250 3550
+F 0 "U?" H 4350 3650 50  0001 C CNN
+F 1 "4027" H 4400 3200 50  0000 C CNN
+F 2 "" H 4250 3550 60  0000 C CNN
+F 3 "" H 4250 3550 60  0000 C CNN
+	1    4250 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L 4027 U?
+U 2 1 5AFDD10B
+P 7350 3550
+F 0 "U?" H 7450 3650 50  0001 C CNN
+F 1 "4027" H 7500 3200 50  0000 C CNN
+F 2 "" H 7350 3550 60  0000 C CNN
+F 3 "" H 7350 3550 60  0000 C CNN
+	2    7350 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L 74LS08 U?
+U 1 1 5AFDD146
+P 5750 3550
+F 0 "U?" H 5750 3600 50  0001 C CNN
+F 1 "74LS08" H 5700 3250 50  0000 C CNN
+F 2 "" H 5750 3550 50  0000 C CNN
+F 3 "" H 5750 3550 50  0000 C CNN
+	1    5750 3550
+	1    0    0    -1  
+$EndComp
+NoConn ~ 7950 3750
+$Comp
+L GND #PWR?
+U 1 1 5AFDD1BB
+P 7350 3000
+F 0 "#PWR?" H 7350 2750 50  0001 C CNN
+F 1 "GND" H 7350 2850 50  0000 C CNN
+F 2 "" H 7350 3000 50  0000 C CNN
+F 3 "" H 7350 3000 50  0000 C CNN
+	1    7350 3000
+	-1   0    0    1   
+$EndComp
+$Comp
+L GND #PWR?
+U 1 1 5AFDD1D5
+P 4250 3000
+F 0 "#PWR?" H 4250 2750 50  0001 C CNN
+F 1 "GND" H 4250 2850 50  0000 C CNN
+F 2 "" H 4250 3000 50  0000 C CNN
+F 3 "" H 4250 3000 50  0000 C CNN
+	1    4250 3000
+	-1   0    0    1   
+$EndComp
+$Comp
+L VCC #PWR?
+U 1 1 5AFDD1F2
+P 3650 3350
+F 0 "#PWR?" H 3650 3200 50  0001 C CNN
+F 1 "VCC" H 3650 3500 50  0000 C CNN
+F 2 "" H 3650 3350 50  0000 C CNN
+F 3 "" H 3650 3350 50  0000 C CNN
+	1    3650 3350
+	0    -1   -1   0   
+$EndComp
+$Comp
+L VCC #PWR?
+U 1 1 5AFDD20C
+P 3650 3750
+F 0 "#PWR?" H 3650 3600 50  0001 C CNN
+F 1 "VCC" H 3650 3900 50  0000 C CNN
+F 2 "" H 3650 3750 50  0000 C CNN
+F 3 "" H 3650 3750 50  0000 C CNN
+	1    3650 3750
+	0    -1   -1   0   
+$EndComp
+$Comp
+L VCC #PWR?
+U 1 1 5AFDD226
+P 6750 3750
+F 0 "#PWR?" H 6750 3600 50  0001 C CNN
+F 1 "VCC" H 6750 3900 50  0000 C CNN
+F 2 "" H 6750 3750 50  0000 C CNN
+F 3 "" H 6750 3750 50  0000 C CNN
+	1    6750 3750
+	0    -1   -1   0   
+$EndComp
+Wire Wire Line
+	6350 3550 6400 3550
+Wire Wire Line
+	6400 3550 6400 3350
+Wire Wire Line
+	6400 3350 6750 3350
+Wire Wire Line
+	4850 3750 5000 3750
+Wire Wire Line
+	5000 3750 5000 3450
+Wire Wire Line
+	5000 3450 5150 3450
+Wire Wire Line
+	5150 4350 5150 3650
+Wire Wire Line
+	2800 4350 5150 4350
+Wire Wire Line
+	7350 4200 7350 4100
+Wire Wire Line
+	2800 4200 7350 4200
+Wire Wire Line
+	4250 4100 4250 4200
+Connection ~ 4250 4200
+Text Label 2800 4200 0    60   ~ 0
+RESET
+Text Label 2800 4350 0    60   ~ 0
+ENABLE
+Text Label 2800 4500 0    60   ~ 0
+CLK
+Wire Wire Line
+	6750 3550 6500 3550
+Wire Wire Line
+	6500 3550 6500 4500
+Wire Wire Line
+	6500 4500 2800 4500
+Wire Wire Line
+	3650 3550 3400 3550
+Wire Wire Line
+	3400 3550 3400 4500
+Connection ~ 3400 4500
+Wire Wire Line
+	4850 3350 4850 4650
+Wire Wire Line
+	4850 4650 8700 4650
+Wire Wire Line
+	7950 3350 8100 3350
+Wire Wire Line
+	8100 3350 8100 4800
+Wire Wire Line
+	8100 4800 8700 4800
+Text Label 8700 4650 2    60   ~ 0
+BASE_CLK
+Text Label 8700 4800 2    60   ~ 0
+CLK1
+$EndSCHEMATC