Add schematic for generating multiple enabled clocks
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188
doc/clock_generation.sch
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188
doc/clock_generation.sch
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EESchema Schematic File Version 2
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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EELAYER 25 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 1 1
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Title ""
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Date ""
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Rev ""
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L 4027 U?
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U 1 1 5AFDD0CA
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P 4250 3550
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F 0 "U?" H 4350 3650 50 0001 C CNN
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F 1 "4027" H 4400 3200 50 0000 C CNN
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F 2 "" H 4250 3550 60 0000 C CNN
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F 3 "" H 4250 3550 60 0000 C CNN
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1 4250 3550
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1 0 0 -1
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$EndComp
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$Comp
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L 4027 U?
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U 2 1 5AFDD10B
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P 7350 3550
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F 0 "U?" H 7450 3650 50 0001 C CNN
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F 1 "4027" H 7500 3200 50 0000 C CNN
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F 2 "" H 7350 3550 60 0000 C CNN
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F 3 "" H 7350 3550 60 0000 C CNN
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2 7350 3550
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1 0 0 -1
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$EndComp
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$Comp
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L 74LS08 U?
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U 1 1 5AFDD146
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P 5750 3550
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F 0 "U?" H 5750 3600 50 0001 C CNN
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F 1 "74LS08" H 5700 3250 50 0000 C CNN
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F 2 "" H 5750 3550 50 0000 C CNN
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F 3 "" H 5750 3550 50 0000 C CNN
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1 5750 3550
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1 0 0 -1
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$EndComp
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NoConn ~ 7950 3750
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$Comp
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L GND #PWR?
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U 1 1 5AFDD1BB
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P 7350 3000
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F 0 "#PWR?" H 7350 2750 50 0001 C CNN
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F 1 "GND" H 7350 2850 50 0000 C CNN
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F 2 "" H 7350 3000 50 0000 C CNN
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F 3 "" H 7350 3000 50 0000 C CNN
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1 7350 3000
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-1 0 0 1
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$EndComp
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$Comp
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L GND #PWR?
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U 1 1 5AFDD1D5
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P 4250 3000
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F 0 "#PWR?" H 4250 2750 50 0001 C CNN
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F 1 "GND" H 4250 2850 50 0000 C CNN
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F 2 "" H 4250 3000 50 0000 C CNN
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F 3 "" H 4250 3000 50 0000 C CNN
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1 4250 3000
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-1 0 0 1
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$EndComp
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$Comp
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L VCC #PWR?
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U 1 1 5AFDD1F2
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P 3650 3350
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F 0 "#PWR?" H 3650 3200 50 0001 C CNN
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F 1 "VCC" H 3650 3500 50 0000 C CNN
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F 2 "" H 3650 3350 50 0000 C CNN
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F 3 "" H 3650 3350 50 0000 C CNN
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1 3650 3350
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0 -1 -1 0
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$EndComp
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$Comp
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L VCC #PWR?
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U 1 1 5AFDD20C
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P 3650 3750
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F 0 "#PWR?" H 3650 3600 50 0001 C CNN
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F 1 "VCC" H 3650 3900 50 0000 C CNN
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F 2 "" H 3650 3750 50 0000 C CNN
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F 3 "" H 3650 3750 50 0000 C CNN
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1 3650 3750
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0 -1 -1 0
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$EndComp
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$Comp
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L VCC #PWR?
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U 1 1 5AFDD226
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P 6750 3750
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F 0 "#PWR?" H 6750 3600 50 0001 C CNN
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F 1 "VCC" H 6750 3900 50 0000 C CNN
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F 2 "" H 6750 3750 50 0000 C CNN
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F 3 "" H 6750 3750 50 0000 C CNN
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1 6750 3750
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0 -1 -1 0
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$EndComp
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Wire Wire Line
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6350 3550 6400 3550
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Wire Wire Line
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6400 3550 6400 3350
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Wire Wire Line
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6400 3350 6750 3350
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Wire Wire Line
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4850 3750 5000 3750
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Wire Wire Line
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5000 3750 5000 3450
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Wire Wire Line
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5000 3450 5150 3450
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Wire Wire Line
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5150 4350 5150 3650
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Wire Wire Line
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2800 4350 5150 4350
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Wire Wire Line
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7350 4200 7350 4100
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Wire Wire Line
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2800 4200 7350 4200
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Wire Wire Line
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4250 4100 4250 4200
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Connection ~ 4250 4200
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Text Label 2800 4200 0 60 ~ 0
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RESET
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Text Label 2800 4350 0 60 ~ 0
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ENABLE
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Text Label 2800 4500 0 60 ~ 0
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CLK
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Wire Wire Line
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6750 3550 6500 3550
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Wire Wire Line
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6500 3550 6500 4500
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Wire Wire Line
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6500 4500 2800 4500
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Wire Wire Line
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3650 3550 3400 3550
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Wire Wire Line
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3400 3550 3400 4500
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Connection ~ 3400 4500
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Wire Wire Line
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4850 3350 4850 4650
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Wire Wire Line
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4850 4650 8700 4650
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Wire Wire Line
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7950 3350 8100 3350
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Wire Wire Line
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8100 3350 8100 4800
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Wire Wire Line
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8100 4800 8700 4800
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Text Label 8700 4650 2 60 ~ 0
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BASE_CLK
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Text Label 8700 4800 2 60 ~ 0
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CLK1
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$EndSCHEMATC
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