Add one- and double-sided pc board

This commit is contained in:
Lena 2018-03-09 00:06:33 +01:00 committed by Klemens Schölhorn
parent 34d4e6c4ce
commit 1e46a456df
9 changed files with 2987 additions and 0 deletions

143
boards/pc/pc-cache.lib Normal file
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# 74LS161
#
DEF 74LS161 U 0 10 Y Y 1 F N
F0 "U" 50 100 50 H V C CNN
F1 "74LS161" 100 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74LS160 74LS162 74LS163
DRAW
X GND 8 -300 -550 0 U 50 50 0 0 W N
X VCC 16 -300 550 0 U 50 50 0 0 W N
S -400 550 400 -550 0 1 0 N
X ~MR 1 -700 -500 300 R 50 50 1 1 I I
X Cp 2 -700 -300 300 R 50 50 1 1 I
X P0 3 -700 200 300 R 50 50 1 1 I
X P1 4 -700 300 300 R 50 50 1 1 I
X P2 5 -700 400 300 R 50 50 1 1 I
X P3 6 -700 500 300 R 50 50 1 1 I
X Cep 7 -700 -100 300 R 50 50 1 1 I
X ~Pe 9 -700 0 300 R 50 50 1 1 I I
X Cet 10 -700 -200 300 R 50 50 1 1 I
X Q3 11 700 200 300 L 50 50 1 1 O
X Q2 12 700 300 300 L 50 50 1 1 O
X Q1 13 700 400 300 L 50 50 1 1 O
X Q0 14 700 500 300 L 50 50 1 1 O
X Tc 15 700 0 300 L 50 50 1 1 O
ENDDRAW
ENDDEF
#
# Conn_01x03
#
DEF Conn_01x03 J 0 40 Y N 1 F N
F0 "J" 0 200 50 H V C CNN
F1 "Conn_01x03" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_??x*mm*
Connector*:*1x??x*mm*
Pin?Header?Straight?1X*
Pin?Header?Angled?1X*
Socket?Strip?Straight?1X*
Socket?Strip?Angled?1X*
$ENDFPLIST
DRAW
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 150 50 -150 1 1 10 f
X Pin_1 1 -200 100 150 R 50 50 1 1 P
X Pin_2 2 -200 0 150 R 50 50 1 1 P
X Pin_3 3 -200 -100 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Conn_01x12
#
DEF Conn_01x12 J 0 40 Y N 1 F N
F0 "J" 0 600 50 H V C CNN
F1 "Conn_01x12" 0 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_??x*mm*
Connector*:*1x??x*mm*
Pin?Header?Straight?1X*
Pin?Header?Angled?1X*
Socket?Strip?Straight?1X*
Socket?Strip?Angled?1X*
$ENDFPLIST
DRAW
S -50 -595 0 -605 1 1 6 N
S -50 -495 0 -505 1 1 6 N
S -50 -395 0 -405 1 1 6 N
S -50 -295 0 -305 1 1 6 N
S -50 -195 0 -205 1 1 6 N
S -50 -95 0 -105 1 1 6 N
S -50 5 0 -5 1 1 6 N
S -50 105 0 95 1 1 6 N
S -50 205 0 195 1 1 6 N
S -50 305 0 295 1 1 6 N
S -50 405 0 395 1 1 6 N
S -50 505 0 495 1 1 6 N
S -50 550 50 -650 1 1 10 f
X Pin_1 1 -200 500 150 R 50 50 1 1 P
X Pin_2 2 -200 400 150 R 50 50 1 1 P
X Pin_3 3 -200 300 150 R 50 50 1 1 P
X Pin_4 4 -200 200 150 R 50 50 1 1 P
X Pin_5 5 -200 100 150 R 50 50 1 1 P
X Pin_6 6 -200 0 150 R 50 50 1 1 P
X Pin_7 7 -200 -100 150 R 50 50 1 1 P
X Pin_8 8 -200 -200 150 R 50 50 1 1 P
X Pin_9 9 -200 -300 150 R 50 50 1 1 P
X Pin_10 10 -200 -400 150 R 50 50 1 1 P
X Pin_11 11 -200 -500 150 R 50 50 1 1 P
X Pin_12 12 -200 -600 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 75 50 H I C CNN
F1 "PWR_FLAG" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
X pwr 1 0 0 0 U 50 50 0 0 w
P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

848
boards/pc/pc.kicad_pcb Normal file
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(kicad_pcb (version 4) (host pcbnew 4.0.7)
(general
(links 45)
(no_connects 1)
(area 134.952381 70.355 162.22762 115.165)
(thickness 1.6)
(drawings 0)
(tracks 263)
(zones 0)
(modules 7)
(nets 34)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
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(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 /Clock)
(net 2 GND)
(net 3 VCC)
(net 4 "Net-(J2-Pad1)")
(net 5 "Net-(J2-Pad2)")
(net 6 "Net-(J2-Pad3)")
(net 7 "Net-(J2-Pad4)")
(net 8 "Net-(J2-Pad5)")
(net 9 "Net-(J2-Pad6)")
(net 10 "Net-(J2-Pad7)")
(net 11 "Net-(J2-Pad8)")
(net 12 "Net-(J2-Pad9)")
(net 13 "Net-(J2-Pad10)")
(net 14 "Net-(J2-Pad11)")
(net 15 "Net-(J2-Pad12)")
(net 16 /Count)
(net 17 /PE)
(net 18 "Net-(J4-Pad1)")
(net 19 "Net-(J4-Pad2)")
(net 20 "Net-(J4-Pad3)")
(net 21 "Net-(J4-Pad4)")
(net 22 "Net-(J4-Pad5)")
(net 23 "Net-(J4-Pad6)")
(net 24 "Net-(J4-Pad7)")
(net 25 "Net-(J4-Pad8)")
(net 26 "Net-(J4-Pad9)")
(net 27 "Net-(J4-Pad10)")
(net 28 "Net-(J4-Pad11)")
(net 29 "Net-(J4-Pad12)")
(net 30 /C0)
(net 31 /C1)
(net 32 "Net-(U3-Pad15)")
(net 33 "Net-(J1-Pad1)")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /C0)
(add_net /C1)
(add_net /Clock)
(add_net /Count)
(add_net /PE)
(add_net GND)
(add_net "Net-(J1-Pad1)")
(add_net "Net-(J2-Pad1)")
(add_net "Net-(J2-Pad10)")
(add_net "Net-(J2-Pad11)")
(add_net "Net-(J2-Pad12)")
(add_net "Net-(J2-Pad2)")
(add_net "Net-(J2-Pad3)")
(add_net "Net-(J2-Pad4)")
(add_net "Net-(J2-Pad5)")
(add_net "Net-(J2-Pad6)")
(add_net "Net-(J2-Pad7)")
(add_net "Net-(J2-Pad8)")
(add_net "Net-(J2-Pad9)")
(add_net "Net-(J4-Pad1)")
(add_net "Net-(J4-Pad10)")
(add_net "Net-(J4-Pad11)")
(add_net "Net-(J4-Pad12)")
(add_net "Net-(J4-Pad2)")
(add_net "Net-(J4-Pad3)")
(add_net "Net-(J4-Pad4)")
(add_net "Net-(J4-Pad5)")
(add_net "Net-(J4-Pad6)")
(add_net "Net-(J4-Pad7)")
(add_net "Net-(J4-Pad8)")
(add_net "Net-(J4-Pad9)")
(add_net "Net-(U3-Pad15)")
(add_net VCC)
)
(module Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm (layer B.Cu) (tedit 59650532) (tstamp 5AA1AE0D)
(at 139.7 111.76)
(descr "Through hole straight pin header, 1x03, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x03 2.54mm single row")
(path /5AA191ED)
(fp_text reference J1 (at 0 2.33) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_01x03 (at 0 -7.41) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -6.35) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -6.35) (end -1.27 -6.35) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -6.35) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.33 -6.41) (end 1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end -1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start 1.33 -1.27) (end 1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -6.85) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -6.85) (end 1.8 -6.85) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -6.85) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 -2.54 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 33 "Net-(J1-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 2 GND))
(pad 3 thru_hole oval (at 0 -5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 VCC))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x03_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm (layer B.Cu) (tedit 59650532) (tstamp 5AA1AE1D)
(at 139.7 73.66 180)
(descr "Through hole straight pin header, 1x12, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x12 2.54mm single row")
(path /5AA16970)
(fp_text reference J2 (at 0 2.33 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_01x12 (at 0 -30.27 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -29.21) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -29.21) (end -1.27 -29.21) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -29.21) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.33 -29.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end -1.33 -29.27) (layer B.SilkS) (width 0.12))
(fp_line (start 1.33 -1.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -29.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -29.75) (end 1.8 -29.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -29.75) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 -13.97 450) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 "Net-(J2-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 "Net-(J2-Pad2)"))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 6 "Net-(J2-Pad3)"))
(pad 4 thru_hole oval (at 0 -7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 7 "Net-(J2-Pad4)"))
(pad 5 thru_hole oval (at 0 -10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 8 "Net-(J2-Pad5)"))
(pad 6 thru_hole oval (at 0 -12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 "Net-(J2-Pad6)"))
(pad 7 thru_hole oval (at 0 -15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 10 "Net-(J2-Pad7)"))
(pad 8 thru_hole oval (at 0 -17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 11 "Net-(J2-Pad8)"))
(pad 9 thru_hole oval (at 0 -20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 12 "Net-(J2-Pad9)"))
(pad 10 thru_hole oval (at 0 -22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 13 "Net-(J2-Pad10)"))
(pad 11 thru_hole oval (at 0 -25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 14 "Net-(J2-Pad11)"))
(pad 12 thru_hole oval (at 0 -27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 "Net-(J2-Pad12)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x12_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm (layer B.Cu) (tedit 59650532) (tstamp 5AA1AE24)
(at 157.48 111.76)
(descr "Through hole straight pin header, 1x03, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x03 2.54mm single row")
(path /5AA19165)
(fp_text reference J3 (at 0 2.33) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_01x03 (at 0 -7.41) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -6.35) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -6.35) (end -1.27 -6.35) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -6.35) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.33 -6.41) (end 1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end -1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start 1.33 -1.27) (end 1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -6.85) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -6.85) (end 1.8 -6.85) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -6.85) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 -2.54 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 16 /Count))
(pad 2 thru_hole oval (at 0 -2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 17 /PE))
(pad 3 thru_hole oval (at 0 -5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 /Clock))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x03_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm (layer B.Cu) (tedit 59650532) (tstamp 5AA1AE34)
(at 157.48 73.66 180)
(descr "Through hole straight pin header, 1x12, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x12 2.54mm single row")
(path /5AA169ED)
(fp_text reference J4 (at 0 2.33 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_01x12 (at 0 -30.27 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -29.21) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -29.21) (end -1.27 -29.21) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -29.21) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.33 -29.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end -1.33 -29.27) (layer B.SilkS) (width 0.12))
(fp_line (start 1.33 -1.27) (end 1.33 -29.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -29.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -29.75) (end 1.8 -29.75) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -29.75) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 -13.97 450) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 18 "Net-(J4-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 19 "Net-(J4-Pad2)"))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 20 "Net-(J4-Pad3)"))
(pad 4 thru_hole oval (at 0 -7.62 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 "Net-(J4-Pad4)"))
(pad 5 thru_hole oval (at 0 -10.16 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 22 "Net-(J4-Pad5)"))
(pad 6 thru_hole oval (at 0 -12.7 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 23 "Net-(J4-Pad6)"))
(pad 7 thru_hole oval (at 0 -15.24 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 24 "Net-(J4-Pad7)"))
(pad 8 thru_hole oval (at 0 -17.78 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 25 "Net-(J4-Pad8)"))
(pad 9 thru_hole oval (at 0 -20.32 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 26 "Net-(J4-Pad9)"))
(pad 10 thru_hole oval (at 0 -22.86 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 27 "Net-(J4-Pad10)"))
(pad 11 thru_hole oval (at 0 -25.4 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 28 "Net-(J4-Pad11)"))
(pad 12 thru_hole oval (at 0 -27.94 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 29 "Net-(J4-Pad12)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x12_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA1AE48)
(at 148.43 80.645)
(descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5AA16657)
(attr smd)
(fp_text reference U1 (at 0 -6) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS161 (at 0 6) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.9 0.9) (thickness 0.135)))
)
(fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 -4.95) (end 1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.7 -5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.7 -5.25) (end 3.7 -5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.7 5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.075 -5.075) (end -2.075 -5.05) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 -5.075) (end 2.075 -4.97) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 5.075) (end 2.075 4.97) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 5.075) (end -2.075 4.97) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 -5.075) (end 2.075 -5.075) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 5.075) (end 2.075 5.075) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 -5.05) (end -3.45 -5.05) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 VCC))
(pad 2 smd rect (at -2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 1 /Clock))
(pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 4 "Net-(J2-Pad1)"))
(pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(J2-Pad2)"))
(pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 "Net-(J2-Pad3)"))
(pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 7 "Net-(J2-Pad4)"))
(pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 16 /Count))
(pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 17 /PE))
(pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 16 /Count))
(pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 21 "Net-(J4-Pad4)"))
(pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 20 "Net-(J4-Pad3)"))
(pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 19 "Net-(J4-Pad2)"))
(pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 18 "Net-(J4-Pad1)"))
(pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 30 /C0))
(pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 VCC))
(model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA1AE5C)
(at 148.59 92.71)
(descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5AA166E3)
(attr smd)
(fp_text reference U2 (at 0 -6) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS161 (at 0 6) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.9 0.9) (thickness 0.135)))
)
(fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 -4.95) (end 1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.7 -5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.7 -5.25) (end 3.7 -5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.7 5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.075 -5.075) (end -2.075 -5.05) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 -5.075) (end 2.075 -4.97) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 5.075) (end 2.075 4.97) (layer F.SilkS) (width 0.15))
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(fp_line (start -2.075 -5.05) (end -3.45 -5.05) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 VCC))
(pad 2 smd rect (at -2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 1 /Clock))
(pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 8 "Net-(J2-Pad5)"))
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(net 9 "Net-(J2-Pad6)"))
(pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 10 "Net-(J2-Pad7)"))
(pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 11 "Net-(J2-Pad8)"))
(pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 30 /C0))
(pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 17 /PE))
(pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 30 /C0))
(pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 25 "Net-(J4-Pad8)"))
(pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 24 "Net-(J4-Pad7)"))
(pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 23 "Net-(J4-Pad6)"))
(pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 22 "Net-(J4-Pad5)"))
(pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 /C1))
(pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 VCC))
(model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA1AE70)
(at 148.43 105.004)
(descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5AA1679F)
(attr smd)
(fp_text reference U3 (at 0 -6) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS161 (at 0 6) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.9 0.9) (thickness 0.135)))
)
(fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15))
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(fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05))
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(fp_line (start -3.7 5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.075 -5.075) (end -2.075 -5.05) (layer F.SilkS) (width 0.15))
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(net 3 VCC))
(pad 2 smd rect (at -2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 1 /Clock))
(pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(J2-Pad9)"))
(pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 13 "Net-(J2-Pad10)"))
(pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 14 "Net-(J2-Pad11)"))
(pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 15 "Net-(J2-Pad12)"))
(pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 /C1))
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(net 2 GND))
(pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 17 /PE))
(pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 /C1))
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(net 32 "Net-(U3-Pad15)"))
(pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 VCC))
(model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
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(segment (start 149.136 86.73091) (end 148.2886 87.57831) (width 0.25) (layer F.Cu) (net 30))
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(segment (start 148.2886 94.4864) (end 146.89 95.885) (width 0.25) (layer F.Cu) (net 30))
(segment (start 146.89 95.885) (end 145.89 95.885) (width 0.25) (layer F.Cu) (net 30))
(segment (start 151.13 77.47) (end 150.0547 77.47) (width 0.25) (layer F.Cu) (net 30))
(segment (start 149.136 78.3887) (end 149.136 84.6123) (width 0.25) (layer F.Cu) (net 30))
(segment (start 150.0547 77.47) (end 149.136 78.3887) (width 0.25) (layer F.Cu) (net 30))
(segment (start 150.0546 108.179) (end 149.393085 107.517485) (width 0.25) (layer F.Cu) (net 31))
(segment (start 149.393085 107.517485) (end 149.393085 103.325815) (width 0.25) (layer F.Cu) (net 31))
(segment (start 149.7644 97.141798) (end 149.7644 89.9853) (width 0.25) (layer F.Cu) (net 31))
(segment (start 149.393085 103.325815) (end 150.2549 102.464) (width 0.25) (layer F.Cu) (net 31))
(segment (start 150.2549 102.464) (end 152.0834 102.464) (width 0.25) (layer F.Cu) (net 31))
(segment (start 152.0834 102.464) (end 152.995042 101.552358) (width 0.25) (layer F.Cu) (net 31))
(segment (start 152.995042 101.552358) (end 152.995042 100.37244) (width 0.25) (layer F.Cu) (net 31))
(segment (start 152.995042 100.37244) (end 149.7644 97.141798) (width 0.25) (layer F.Cu) (net 31))
(segment (start 150.2147 89.535) (end 151.29 89.535) (width 0.25) (layer F.Cu) (net 31))
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)

63
boards/pc/pc.pro Normal file
View File

@ -0,0 +1,63 @@
update=2018-03-08T17:33:13 CET
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=switches
LibName4=relays
LibName5=motors
LibName6=transistors
LibName7=conn
LibName8=linear
LibName9=regul
LibName10=74xx
LibName11=cmos4000
LibName12=adc-dac
LibName13=memory
LibName14=xilinx
LibName15=microcontrollers
LibName16=dsp
LibName17=microchip
LibName18=analog_switches
LibName19=motorola
LibName20=texas
LibName21=intel
LibName22=audio
LibName23=interface
LibName24=digital-audio
LibName25=philips
LibName26=display
LibName27=cypress
LibName28=siliconi
LibName29=opto
LibName30=atmel
LibName31=contrib
LibName32=valves
[general]
version=1

398
boards/pc/pc.sch Normal file
View File

@ -0,0 +1,398 @@
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:switches
LIBS:relays
LIBS:motors
LIBS:transistors
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LIBS:linear
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LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
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LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:pc-cache
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View File

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EESchema-LIBRARY Version 2.3
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#
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F0 "U" 50 100 50 H V C CNN
F1 "74LS161" 100 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS 74LS160 74LS162 74LS163
DRAW
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#
# Conn_01x03
#
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F0 "J" 0 200 50 H V C CNN
F1 "Conn_01x03" 0 -200 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Connector*:*_??x*mm*
Connector*:*1x??x*mm*
Pin?Header?Straight?1X*
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Socket?Strip?Angled?1X*
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DRAW
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ENDDEF
#
# Conn_01x12
#
DEF Conn_01x12 J 0 40 Y N 1 F N
F0 "J" 0 600 50 H V C CNN
F1 "Conn_01x12" 0 -700 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
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Connector*:*1x??x*mm*
Pin?Header?Straight?1X*
Pin?Header?Angled?1X*
Socket?Strip?Straight?1X*
Socket?Strip?Angled?1X*
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DRAW
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#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
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ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
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F1 "PWR_FLAG" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
X pwr 1 0 0 0 U 50 50 0 0 w
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ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
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F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
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ENDDEF
#
#End Library

View File

@ -0,0 +1,851 @@
(kicad_pcb (version 4) (host pcbnew 4.0.7)
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)
(page A4)
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(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
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(43 Eco2.User user)
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(net 0 "")
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(net 2 GND)
(net 3 VCC)
(net 4 "Net-(J2-Pad1)")
(net 5 "Net-(J2-Pad2)")
(net 6 "Net-(J2-Pad3)")
(net 7 "Net-(J2-Pad4)")
(net 8 "Net-(J2-Pad5)")
(net 9 "Net-(J2-Pad6)")
(net 10 "Net-(J2-Pad7)")
(net 11 "Net-(J2-Pad8)")
(net 12 "Net-(J2-Pad9)")
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(net 14 "Net-(J2-Pad11)")
(net 15 "Net-(J2-Pad12)")
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(net 20 "Net-(J4-Pad2)")
(net 21 "Net-(J4-Pad3)")
(net 22 "Net-(J4-Pad4)")
(net 23 "Net-(J4-Pad5)")
(net 24 "Net-(J4-Pad6)")
(net 25 "Net-(J4-Pad7)")
(net 26 "Net-(J4-Pad8)")
(net 27 "Net-(J4-Pad9)")
(net 28 "Net-(J4-Pad10)")
(net 29 "Net-(J4-Pad11)")
(net 30 "Net-(J4-Pad12)")
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(net_class Default "This is the default net class."
(clearance 0.3)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /C0)
(add_net /C1)
(add_net /Clock)
(add_net /Count)
(add_net /PE)
(add_net GND)
(add_net "Net-(J1-Pad1)")
(add_net "Net-(J2-Pad1)")
(add_net "Net-(J2-Pad10)")
(add_net "Net-(J2-Pad11)")
(add_net "Net-(J2-Pad12)")
(add_net "Net-(J2-Pad2)")
(add_net "Net-(J2-Pad3)")
(add_net "Net-(J2-Pad4)")
(add_net "Net-(J2-Pad5)")
(add_net "Net-(J2-Pad6)")
(add_net "Net-(J2-Pad7)")
(add_net "Net-(J2-Pad8)")
(add_net "Net-(J2-Pad9)")
(add_net "Net-(J4-Pad1)")
(add_net "Net-(J4-Pad10)")
(add_net "Net-(J4-Pad11)")
(add_net "Net-(J4-Pad12)")
(add_net "Net-(J4-Pad2)")
(add_net "Net-(J4-Pad3)")
(add_net "Net-(J4-Pad4)")
(add_net "Net-(J4-Pad5)")
(add_net "Net-(J4-Pad6)")
(add_net "Net-(J4-Pad7)")
(add_net "Net-(J4-Pad8)")
(add_net "Net-(J4-Pad9)")
(add_net "Net-(U3-Pad15)")
(add_net VCC)
)
(module Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm (layer B.Cu) (tedit 59650532) (tstamp 5AA1B714)
(at 142.24 127)
(descr "Through hole straight pin header, 1x03, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x03 2.54mm single row")
(path /5AA191ED)
(fp_text reference J1 (at 0 2.33) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_01x03 (at 0 -7.41) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -6.35) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -6.35) (end -1.27 -6.35) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -6.35) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.33 -6.41) (end 1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end -1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start 1.33 -1.27) (end 1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -6.85) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -6.85) (end 1.8 -6.85) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -6.85) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 -2.54 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 1 "Net-(J1-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 2 GND))
(pad 3 thru_hole oval (at 0 -5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 VCC))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x03_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm (layer F.Cu) (tedit 59650532) (tstamp 5AA1B734)
(at 142.24 88.9)
(descr "Through hole straight pin header, 1x12, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x12 2.54mm single row")
(path /5AA16970)
(fp_text reference J2 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x12 (at 0 30.27) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 29.21) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 29.21) (end -1.27 29.21) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 29.21) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 29.27) (end 1.33 29.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 29.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 29.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 29.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 29.75) (end 1.8 29.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 29.75) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 13.97 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 4 "Net-(J2-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 5 "Net-(J2-Pad2)"))
(pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 6 "Net-(J2-Pad3)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 7 "Net-(J2-Pad4)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 8 "Net-(J2-Pad5)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 9 "Net-(J2-Pad6)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 10 "Net-(J2-Pad7)"))
(pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 11 "Net-(J2-Pad8)"))
(pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 12 "Net-(J2-Pad9)"))
(pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 13 "Net-(J2-Pad10)"))
(pad 11 thru_hole oval (at 0 25.4) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 14 "Net-(J2-Pad11)"))
(pad 12 thru_hole oval (at 0 27.94) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 15 "Net-(J2-Pad12)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x12_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm (layer B.Cu) (tedit 59650532) (tstamp 5AA1B74B)
(at 160.02 127)
(descr "Through hole straight pin header, 1x03, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x03 2.54mm single row")
(path /5AA19165)
(fp_text reference J3 (at 0 2.33) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value Conn_01x03 (at 0 -7.41) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.635 1.27) (end 1.27 1.27) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -6.35) (layer B.Fab) (width 0.1))
(fp_line (start 1.27 -6.35) (end -1.27 -6.35) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 -6.35) (end -1.27 0.635) (layer B.Fab) (width 0.1))
(fp_line (start -1.27 0.635) (end -0.635 1.27) (layer B.Fab) (width 0.1))
(fp_line (start -1.33 -6.41) (end 1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end -1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start 1.33 -1.27) (end 1.33 -6.41) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 -1.27) (end 1.33 -1.27) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 0 1.33) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 1.8) (end -1.8 -6.85) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 -6.85) (end 1.8 -6.85) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -6.85) (end 1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end -1.8 1.8) (layer B.CrtYd) (width 0.05))
(fp_text user %R (at 0 -2.54 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 16 /Count))
(pad 2 thru_hole oval (at 0 -2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 17 /PE))
(pad 3 thru_hole oval (at 0 -5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 18 /Clock))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x03_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm (layer F.Cu) (tedit 59650532) (tstamp 5AA1B76B)
(at 160.02 88.9)
(descr "Through hole straight pin header, 1x12, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x12 2.54mm single row")
(path /5AA169ED)
(fp_text reference J4 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x12 (at 0 30.27) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 29.21) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 29.21) (end -1.27 29.21) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 29.21) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 29.27) (end 1.33 29.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 29.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 29.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 29.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 29.75) (end 1.8 29.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 29.75) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 13.97 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 19 "Net-(J4-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 20 "Net-(J4-Pad2)"))
(pad 3 thru_hole oval (at 0 5.08) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 21 "Net-(J4-Pad3)"))
(pad 4 thru_hole oval (at 0 7.62) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 22 "Net-(J4-Pad4)"))
(pad 5 thru_hole oval (at 0 10.16) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 23 "Net-(J4-Pad5)"))
(pad 6 thru_hole oval (at 0 12.7) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 24 "Net-(J4-Pad6)"))
(pad 7 thru_hole oval (at 0 15.24) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 25 "Net-(J4-Pad7)"))
(pad 8 thru_hole oval (at 0 17.78) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 26 "Net-(J4-Pad8)"))
(pad 9 thru_hole oval (at 0 20.32) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 27 "Net-(J4-Pad9)"))
(pad 10 thru_hole oval (at 0 22.86) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 28 "Net-(J4-Pad10)"))
(pad 11 thru_hole oval (at 0 25.4) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 29 "Net-(J4-Pad11)"))
(pad 12 thru_hole oval (at 0 27.94) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 30 "Net-(J4-Pad12)"))
(model ${KISYS3DMOD}/Pin_Headers.3dshapes/Pin_Header_Straight_1x12_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA1B790)
(at 151.29 95.885)
(descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5AA16657)
(attr smd)
(fp_text reference U1 (at 0 -6) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS161 (at 0 6) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.9 0.9) (thickness 0.135)))
)
(fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 -4.95) (end 1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.7 -5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.7 -5.25) (end 3.7 -5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.7 5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.075 -5.075) (end -2.075 -5.05) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 -5.075) (end 2.075 -4.97) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 5.075) (end 2.075 4.97) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 5.075) (end -2.075 4.97) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 -5.075) (end 2.075 -5.075) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 5.075) (end 2.075 5.075) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 -5.05) (end -3.45 -5.05) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 VCC))
(pad 2 smd rect (at -2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 18 /Clock))
(pad 3 smd rect (at -2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 4 "Net-(J2-Pad1)"))
(pad 4 smd rect (at -2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(J2-Pad2)"))
(pad 5 smd rect (at -2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 "Net-(J2-Pad3)"))
(pad 6 smd rect (at -2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 7 "Net-(J2-Pad4)"))
(pad 7 smd rect (at -2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 16 /Count))
(pad 8 smd rect (at -2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 9 smd rect (at 2.7 4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 17 /PE))
(pad 10 smd rect (at 2.7 3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 16 /Count))
(pad 11 smd rect (at 2.7 1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 22 "Net-(J4-Pad4)"))
(pad 12 smd rect (at 2.7 0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 21 "Net-(J4-Pad3)"))
(pad 13 smd rect (at 2.7 -0.635) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 20 "Net-(J4-Pad2)"))
(pad 14 smd rect (at 2.7 -1.905) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 19 "Net-(J4-Pad1)"))
(pad 15 smd rect (at 2.7 -3.175) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 /C0))
(pad 16 smd rect (at 2.7 -4.445) (size 1.5 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 VCC))
(model ${KISYS3DMOD}/Housings_SOIC.3dshapes/SOIC-16_3.9x9.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA1B7B5)
(at 151.29 107.315)
(descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5AA166E3)
(attr smd)
(fp_text reference U2 (at 0 -6) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS161 (at 0 6) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.9 0.9) (thickness 0.135)))
)
(fp_line (start -0.95 -4.95) (end 1.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 -4.95) (end 1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 4.95) (end -1.95 4.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 4.95) (end -1.95 -3.95) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 -3.95) (end -0.95 -4.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.7 -5.25) (end -3.7 5.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.7 -5.25) (end 3.7 5.25) (layer F.CrtYd) (width 0.05))
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(module Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm (layer F.Cu) (tedit 58CC8F64) (tstamp 5AA1B7DA)
(at 151.13 119.38)
(descr "16-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5AA1679F)
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(segment (start 155.1653 93.7547) (end 160.02 88.9) (width 0.25) (layer F.Cu) (net 19))
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(segment (start 157.4747 97.79) (end 158.7447 96.52) (width 0.25) (layer F.Cu) (net 22))
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(segment (start 148.43 122.555) (end 146.5725 122.555) (width 0.25) (layer F.Cu) (net 32))
)

63
boards/pc_double/pc.pro Normal file
View File

@ -0,0 +1,63 @@
update=2018-03-08T17:33:13 CET
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=switches
LibName4=relays
LibName5=motors
LibName6=transistors
LibName7=conn
LibName8=linear
LibName9=regul
LibName10=74xx
LibName11=cmos4000
LibName12=adc-dac
LibName13=memory
LibName14=xilinx
LibName15=microcontrollers
LibName16=dsp
LibName17=microchip
LibName18=analog_switches
LibName19=motorola
LibName20=texas
LibName21=intel
LibName22=audio
LibName23=interface
LibName24=digital-audio
LibName25=philips
LibName26=display
LibName27=cypress
LibName28=siliconi
LibName29=opto
LibName30=atmel
LibName31=contrib
LibName32=valves
[general]
version=1

80
boards/pc_double/pc.rules Normal file
View File

@ -0,0 +1,80 @@
(rules PCB pc
(snap_angle
fortyfive_degree
)
(autoroute_settings
(fanout off)
(autoroute on)
(postroute on)
(vias on)
(via_costs 50)
(plane_via_costs 5)
(start_ripup_costs 100)
(start_pass_no 1177)
(layer_rule F.Cu
(active on)
(preferred_direction vertical)
(preferred_direction_trace_costs 1.0)
(against_preferred_direction_trace_costs 2.8)
)
(layer_rule B.Cu
(active on)
(preferred_direction horizontal)
(preferred_direction_trace_costs 1.0)
(against_preferred_direction_trace_costs 1.6)
)
)
(rule
(width 250.0)
(clear 300.2)
(clear 125.0 (type smd_to_turn_gap))
(clear 75.0 (type smd_smd))
)
(padstack "Via[0-1]_600:400_um"
(shape
(circle F.Cu 600.0 0.0 0.0)
)
(shape
(circle B.Cu 600.0 0.0 0.0)
)
(attach off)
)
(via
"Via[0-1]_600:400_um" "Via[0-1]_600:400_um" default
)
(via
"Via[0-1]_600:400_um-kicad_default" "Via[0-1]_600:400_um" "kicad_default"
)
(via_rule
default "Via[0-1]_600:400_um"
)
(via_rule
"kicad_default" "Via[0-1]_600:400_um-kicad_default"
)
(class default
(clearance_class default)
(via_rule default)
(rule
(width 250.0)
)
(circuit
(use_layer F.Cu B.Cu)
)
)
(class "kicad_default"
"Net-(J1-Pad1)" GND VCC "Net-(J2-Pad1)" "Net-(J2-Pad2)" "Net-(J2-Pad3)" "Net-(J2-Pad4)" "Net-(J2-Pad5)"
"Net-(J2-Pad6)" "Net-(J2-Pad7)" "Net-(J2-Pad8)" "Net-(J2-Pad9)" "Net-(J2-Pad10)" "Net-(J2-Pad11)" "Net-(J2-Pad12)" /Count
/PE /Clock "Net-(J4-Pad1)" "Net-(J4-Pad2)" "Net-(J4-Pad3)" "Net-(J4-Pad4)" "Net-(J4-Pad5)" "Net-(J4-Pad6)"
"Net-(J4-Pad7)" "Net-(J4-Pad8)" "Net-(J4-Pad9)" "Net-(J4-Pad10)" "Net-(J4-Pad11)" "Net-(J4-Pad12)" /C0 /C1
"Net-(U3-Pad15)"
(clearance_class "kicad_default")
(via_rule kicad_default)
(rule
(width 250.0)
)
(circuit
(use_layer F.Cu B.Cu)
)
)
)

398
boards/pc_double/pc.sch Normal file
View File

@ -0,0 +1,398 @@
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:switches
LIBS:relays
LIBS:motors
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:pc-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 1
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L 74LS161 U1
U 1 1 5AA16657
P 4900 2250
F 0 "U1" H 4950 2350 50 0000 C CNN
F 1 "74LS161" H 5000 2050 50 0000 C CNN
F 2 "Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm" H 4900 2250 50 0001 C CNN
F 3 "" H 4900 2250 50 0001 C CNN
1 4900 2250
1 0 0 -1
$EndComp
$Comp
L 74LS161 U3
U 1 1 5AA1679F
P 4900 5700
F 0 "U3" H 4950 5800 50 0000 C CNN
F 1 "74LS161" H 5000 5500 50 0000 C CNN
F 2 "Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm" H 4900 5700 50 0001 C CNN
F 3 "" H 4900 5700 50 0001 C CNN
1 4900 5700
1 0 0 -1
$EndComp
$Comp
L Conn_01x12 J2
U 1 1 5AA16970
P 2600 4000
F 0 "J2" H 2600 4600 50 0000 C CNN
F 1 "Conn_01x12" H 2600 3300 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm" H 2600 4000 50 0001 C CNN
F 3 "" H 2600 4000 50 0001 C CNN
1 2600 4000
-1 0 0 -1
$EndComp
$Comp
L Conn_01x12 J4
U 1 1 5AA169ED
P 7350 3950
F 0 "J4" H 7350 4550 50 0000 C CNN
F 1 "Conn_01x12" H 7350 3250 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_1x12_Pitch2.54mm" H 7350 3950 50 0001 C CNN
F 3 "" H 7350 3950 50 0001 C CNN
1 7350 3950
1 0 0 -1
$EndComp
Wire Wire Line
2800 3500 3550 3500
Wire Wire Line
3550 3500 3550 2050
Wire Wire Line
3550 2050 4200 2050
Wire Wire Line
4200 1950 3500 1950
Wire Wire Line
3500 1950 3500 3600
Wire Wire Line
3500 3600 2800 3600
Wire Wire Line
2800 3700 3450 3700
Wire Wire Line
3450 3700 3450 1850
Wire Wire Line
3450 1850 4200 1850
Wire Wire Line
4200 1750 3400 1750
Wire Wire Line
3400 1750 3400 3800
Wire Wire Line
3400 3800 2800 3800
Wire Wire Line
2800 3900 3950 3900
Wire Wire Line
3950 3900 3950 3750
Wire Wire Line
3950 3750 4200 3750
Wire Wire Line
4200 3650 3900 3650
Wire Wire Line
3900 3650 3900 4000
Wire Wire Line
3900 4000 2800 4000
Wire Wire Line
2800 4100 3850 4100
Wire Wire Line
3850 4100 3850 3550
Wire Wire Line
3850 3550 4200 3550
Wire Wire Line
4200 3450 3800 3450
Wire Wire Line
3800 3450 3800 4200
Wire Wire Line
3800 4200 2800 4200
Wire Wire Line
2800 4300 3400 4300
Wire Wire Line
3400 4300 3400 5500
Wire Wire Line
3450 5400 3450 4400
Wire Wire Line
3450 4400 2800 4400
Wire Wire Line
2800 4500 3500 4500
Wire Wire Line
3500 4500 3500 5300
Wire Wire Line
3550 4600 3550 5200
Wire Wire Line
2800 4600 3550 4600
Wire Wire Line
3400 5500 4200 5500
Wire Wire Line
4200 5400 3450 5400
Wire Wire Line
3500 5300 4200 5300
Wire Wire Line
3550 5200 4200 5200
Wire Wire Line
5600 5500 6550 5500
Wire Wire Line
6550 5500 6550 4550
Wire Wire Line
6550 4550 7150 4550
Wire Wire Line
7150 4450 6500 4450
Wire Wire Line
6500 4450 6500 5400
Wire Wire Line
6500 5400 5600 5400
Wire Wire Line
5600 5300 6450 5300
Wire Wire Line
6450 5300 6450 4350
Wire Wire Line
6450 4350 7150 4350
Wire Wire Line
7150 4250 6400 4250
Wire Wire Line
6400 4250 6400 5200
Wire Wire Line
6400 5200 5600 5200
Wire Wire Line
7150 4150 6400 4150
Wire Wire Line
6400 4150 6400 3750
Wire Wire Line
6400 3750 5600 3750
Wire Wire Line
5600 3650 6450 3650
Wire Wire Line
6450 3650 6450 4050
Wire Wire Line
6450 4050 7150 4050
Wire Wire Line
7150 3950 6500 3950
Wire Wire Line
6500 3950 6500 3550
Wire Wire Line
6500 3550 5600 3550
Wire Wire Line
5600 3450 6550 3450
Wire Wire Line
6550 3450 6550 3850
Wire Wire Line
6550 3850 7150 3850
Wire Wire Line
5600 2050 6750 2050
Wire Wire Line
6750 2050 6750 3750
Wire Wire Line
6750 3750 7150 3750
Wire Wire Line
7150 3650 6800 3650
Wire Wire Line
6800 3650 6800 1950
Wire Wire Line
6800 1950 5600 1950
Wire Wire Line
5600 1850 6850 1850
Wire Wire Line
6850 1850 6850 3550
Wire Wire Line
6850 3550 7150 3550
Wire Wire Line
7150 3450 6900 3450
Wire Wire Line
6900 3450 6900 1750
Wire Wire Line
6900 1750 5600 1750
$Comp
L VCC #PWR01
U 1 1 5AA17719
P 2800 3100
F 0 "#PWR01" H 2800 2950 50 0001 C CNN
F 1 "VCC" H 2800 3250 50 0000 C CNN
F 2 "" H 2800 3100 50 0001 C CNN
F 3 "" H 2800 3100 50 0001 C CNN
1 2800 3100
-1 0 0 1
$EndComp
$Comp
L GND #PWR02
U 1 1 5AA17667
P 3000 3000
F 0 "#PWR02" H 3000 2750 50 0001 C CNN
F 1 "GND" H 3000 2850 50 0000 C CNN
F 2 "" H 3000 3000 50 0001 C CNN
F 3 "" H 3000 3000 50 0001 C CNN
1 3000 3000
1 0 0 -1
$EndComp
$Comp
L 74LS161 U2
U 1 1 5AA166E3
P 4900 3950
F 0 "U2" H 4950 4050 50 0000 C CNN
F 1 "74LS161" H 5000 3750 50 0000 C CNN
F 2 "Housings_SOIC:SOIC-16_3.9x9.9mm_Pitch1.27mm" H 4900 3950 50 0001 C CNN
F 3 "" H 4900 3950 50 0001 C CNN
1 4900 3950
1 0 0 -1
$EndComp
Text Label 5600 2250 0 60 ~ 0
C0
Text Label 4200 4050 0 60 ~ 0
C0
Text Label 4200 4150 0 60 ~ 0
C0
Text Label 5600 3950 0 60 ~ 0
C1
Text Label 4200 5800 0 60 ~ 0
C1
Text Label 4200 5900 0 60 ~ 0
C1
Wire Wire Line
2300 3000 3000 3000
Wire Wire Line
2300 3100 2800 3100
Text Label 4200 2750 0 60 ~ 0
Reset
Text Label 4200 2350 0 60 ~ 0
Count
Text Label 4200 2450 0 60 ~ 0
Count
Text Label 4200 2250 0 60 ~ 0
PE
Text Label 4200 2550 0 60 ~ 0
Clock
Text Label 4200 3950 0 60 ~ 0
PE
Text Label 4200 4250 0 60 ~ 0
Clock
Text Label 4200 4450 0 60 ~ 0
Reset
Text Label 4200 5700 0 60 ~ 0
PE
Text Label 4200 6000 0 60 ~ 0
Clock
Text Label 4200 6200 0 60 ~ 0
Reset
$Comp
L Conn_01x03 J3
U 1 1 5AA19165
P 7300 2600
F 0 "J3" H 7300 2800 50 0000 C CNN
F 1 "Conn_01x03" H 7300 2400 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm" H 7300 2600 50 0001 C CNN
F 3 "" H 7300 2600 50 0001 C CNN
1 7300 2600
1 0 0 -1
$EndComp
Text Label 7100 2500 0 60 ~ 0
Count
Text Label 7100 2600 0 60 ~ 0
PE
$Comp
L Conn_01x03 J1
U 1 1 5AA191ED
P 2100 3000
F 0 "J1" H 2100 3200 50 0000 C CNN
F 1 "Conn_01x03" H 2100 2800 50 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_1x03_Pitch2.54mm" H 2100 3000 50 0001 C CNN
F 3 "" H 2100 3000 50 0001 C CNN
1 2100 3000
-1 0 0 -1
$EndComp
Text Label 2300 3000 0 60 ~ 0
GND
Text Label 2300 3100 0 60 ~ 0
VCC
NoConn ~ 5600 5700
$Comp
L PWR_FLAG #FLG03
U 1 1 5AA1975B
P 1750 4850
F 0 "#FLG03" H 1750 4925 50 0001 C CNN
F 1 "PWR_FLAG" H 1750 5000 50 0000 C CNN
F 2 "" H 1750 4850 50 0001 C CNN
F 3 "" H 1750 4850 50 0001 C CNN
1 1750 4850
1 0 0 -1
$EndComp
$Comp
L GND #PWR04
U 1 1 5AA19792
P 1750 4850
F 0 "#PWR04" H 1750 4600 50 0001 C CNN
F 1 "GND" H 1750 4700 50 0000 C CNN
F 2 "" H 1750 4850 50 0001 C CNN
F 3 "" H 1750 4850 50 0001 C CNN
1 1750 4850
1 0 0 -1
$EndComp
$Comp
L PWR_FLAG #FLG05
U 1 1 5AA197B9
P 1100 5500
F 0 "#FLG05" H 1100 5575 50 0001 C CNN
F 1 "PWR_FLAG" H 1100 5650 50 0000 C CNN
F 2 "" H 1100 5500 50 0001 C CNN
F 3 "" H 1100 5500 50 0001 C CNN
1 1100 5500
-1 0 0 1
$EndComp
$Comp
L VCC #PWR06
U 1 1 5AA197DB
P 1100 5500
F 0 "#PWR06" H 1100 5350 50 0001 C CNN
F 1 "VCC" H 1100 5650 50 0000 C CNN
F 2 "" H 1100 5500 50 0001 C CNN
F 3 "" H 1100 5500 50 0001 C CNN
1 1100 5500
1 0 0 -1
$EndComp
Text Label 7100 2700 0 60 ~ 0
Clock
NoConn ~ 2300 2900
Text Label 3900 2750 0 60 ~ 0
VCC
Text Label 3900 4450 0 60 ~ 0
VCC
Text Label 3900 6200 0 60 ~ 0
VCC
Wire Wire Line
3900 2750 4200 2750
Wire Wire Line
3900 4450 4200 4450
Wire Wire Line
3900 6200 4200 6200
$EndSCHEMATC