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Import register board

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This commit is contained in:
Klemens Schölhorn 2018-03-09 00:19:02 +01:00
parent bd47c5633f
commit 34d4e6c4ce
4 changed files with 1235 additions and 0 deletions
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132
boards/register/register-cache.lib Normal file
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# 74LS574
#
DEF 74LS574 U 0 40 Y Y 1 F N
F0 "U" 0 0 50 H V C CNN
F1 "74LS574" 50 -350 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
X GND 10 0 -550 0 U 50 50 0 0 W N
X VCC 20 0 550 0 D 50 50 0 0 W N
S -400 550 400 -550 0 1 0 N
X OE 1 -700 -500 300 R 50 50 1 1 I I
X D0 2 -700 500 300 R 50 50 1 1 I
X D1 3 -700 400 300 R 50 50 1 1 I
X D2 4 -700 300 300 R 50 50 1 1 I
X D3 5 -700 200 300 R 50 50 1 1 I
X D4 6 -700 100 300 R 50 50 1 1 I
X D5 7 -700 0 300 R 50 50 1 1 I
X D6 8 -700 -100 300 R 50 50 1 1 I
X D7 9 -700 -200 300 R 50 50 1 1 I
X Cp 11 -700 -400 300 R 50 50 1 1 I C
X Q7 12 700 -200 300 L 50 50 1 1 T
X Q6 13 700 -100 300 L 50 50 1 1 T
X Q5 14 700 0 300 L 50 50 1 1 T
X Q4 15 700 100 300 L 50 50 1 1 T
X Q3 16 700 200 300 L 50 50 1 1 T
X Q2 17 700 300 300 L 50 50 1 1 T
X Q1 18 700 400 300 L 50 50 1 1 T
X Q0 19 700 500 300 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# CONN_01X02
#
DEF CONN_01X02 P 0 40 Y N 1 F N
F0 "P" 0 150 50 H V C CNN
F1 "CONN_01X02" 100 0 50 V V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Pin_Header_Straight_1X02
Pin_Header_Angled_1X02
Socket_Strip_Straight_1X02
Socket_Strip_Angled_1X02
$ENDFPLIST
DRAW
S -50 -45 10 -55 0 1 0 N
S -50 55 10 45 0 1 0 N
S -50 100 50 -100 0 1 0 N
X P1 1 -200 50 150 R 50 50 1 1 P
X P2 2 -200 -50 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X08
#
DEF CONN_01X08 P 0 40 Y N 1 F N
F0 "P" 0 450 50 H V C CNN
F1 "CONN_01X08" 100 0 50 V V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
$FPLIST
Pin_Header_Straight_1X08
Pin_Header_Angled_1X08
Socket_Strip_Straight_1X08
Socket_Strip_Angled_1X08
$ENDFPLIST
DRAW
S -50 -400 50 400 0 1 0 N
S -50 -345 10 -355 0 1 0 N
S -50 -245 10 -255 0 1 0 N
S -50 -145 10 -155 0 1 0 N
S -50 -45 10 -55 0 1 0 N
S -50 55 10 45 0 1 0 N
S -50 155 10 145 0 1 0 N
S -50 255 10 245 0 1 0 N
S -50 355 10 345 0 1 0 N
X P1 1 -200 350 150 R 50 50 1 1 P
X P2 2 -200 250 150 R 50 50 1 1 P
X P3 3 -200 150 150 R 50 50 1 1 P
X P4 4 -200 50 150 R 50 50 1 1 P
X P5 5 -200 -50 150 R 50 50 1 1 P
X P6 6 -200 -150 150 R 50 50 1 1 P
X P7 7 -200 -250 150 R 50 50 1 1 P
X P8 8 -200 -350 150 R 50 50 1 1 P
ENDDRAW
ENDDEF
#
# GND
#
DEF GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# PWR_FLAG
#
DEF PWR_FLAG #FLG 0 0 N N 1 F P
F0 "#FLG" 0 95 50 H I C CNN
F1 "PWR_FLAG" 0 180 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
X pwr 1 0 0 0 U 50 50 0 0 w
P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
ENDDRAW
ENDDEF
#
# VCC
#
DEF VCC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "VCC" 0 150 50 H V C CNN
F2 "" 0 0 50 H V C CNN
F3 "" 0 0 50 H V C CNN
DRAW
C 0 75 25 0 1 0 N
P 2 0 1 0 0 0 0 50 N
X VCC 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

832
boards/register/register.kicad_pcb Normal file
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@ -0,0 +1,832 @@
(kicad_pcb (version 4) (host pcbnew 4.0.2+dfsg1-stable)
(general
(links 40)
(no_connects 0)
(area 132.051667 85.215 160.048334 140.695)
(thickness 1.6)
(drawings 0)
(tracks 152)
(zones 0)
(modules 8)
(nets 37)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.25)
(trace_clearance 0.2)
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 2.032 2.032)
(pad_drill 1.016)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x00000_00000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 4)
(mirror true)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 /CLK)
(net 2 "Net-(P1-Pad2)")
(net 3 "Net-(P2-Pad1)")
(net 4 "Net-(P2-Pad2)")
(net 5 "Net-(P2-Pad3)")
(net 6 "Net-(P2-Pad4)")
(net 7 "Net-(P2-Pad5)")
(net 8 "Net-(P2-Pad6)")
(net 9 "Net-(P2-Pad7)")
(net 10 "Net-(P2-Pad8)")
(net 11 "Net-(P3-Pad1)")
(net 12 "Net-(P3-Pad2)")
(net 13 "Net-(P3-Pad3)")
(net 14 "Net-(P3-Pad4)")
(net 15 "Net-(P3-Pad5)")
(net 16 "Net-(P3-Pad6)")
(net 17 "Net-(P3-Pad7)")
(net 18 "Net-(P3-Pad8)")
(net 19 VCC)
(net 20 GND)
(net 21 "Net-(P5-Pad1)")
(net 22 "Net-(P5-Pad2)")
(net 23 "Net-(P5-Pad3)")
(net 24 "Net-(P5-Pad4)")
(net 25 "Net-(P5-Pad5)")
(net 26 "Net-(P5-Pad6)")
(net 27 "Net-(P5-Pad7)")
(net 28 "Net-(P5-Pad8)")
(net 29 "Net-(P6-Pad1)")
(net 30 "Net-(P6-Pad2)")
(net 31 "Net-(P6-Pad3)")
(net 32 "Net-(P6-Pad4)")
(net 33 "Net-(P6-Pad5)")
(net 34 "Net-(P6-Pad6)")
(net 35 "Net-(P6-Pad7)")
(net 36 "Net-(P6-Pad8)")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net /CLK)
(add_net GND)
(add_net "Net-(P1-Pad2)")
(add_net "Net-(P2-Pad1)")
(add_net "Net-(P2-Pad2)")
(add_net "Net-(P2-Pad3)")
(add_net "Net-(P2-Pad4)")
(add_net "Net-(P2-Pad5)")
(add_net "Net-(P2-Pad6)")
(add_net "Net-(P2-Pad7)")
(add_net "Net-(P2-Pad8)")
(add_net "Net-(P3-Pad1)")
(add_net "Net-(P3-Pad2)")
(add_net "Net-(P3-Pad3)")
(add_net "Net-(P3-Pad4)")
(add_net "Net-(P3-Pad5)")
(add_net "Net-(P3-Pad6)")
(add_net "Net-(P3-Pad7)")
(add_net "Net-(P3-Pad8)")
(add_net "Net-(P5-Pad1)")
(add_net "Net-(P5-Pad2)")
(add_net "Net-(P5-Pad3)")
(add_net "Net-(P5-Pad4)")
(add_net "Net-(P5-Pad5)")
(add_net "Net-(P5-Pad6)")
(add_net "Net-(P5-Pad7)")
(add_net "Net-(P5-Pad8)")
(add_net "Net-(P6-Pad1)")
(add_net "Net-(P6-Pad2)")
(add_net "Net-(P6-Pad3)")
(add_net "Net-(P6-Pad4)")
(add_net "Net-(P6-Pad5)")
(add_net "Net-(P6-Pad6)")
(add_net "Net-(P6-Pad7)")
(add_net "Net-(P6-Pad8)")
(add_net VCC)
)
(module Pin_Headers:Pin_Header_Straight_1x02 (layer B.Cu) (tedit 5AA16CB7) (tstamp 5AA26C74)
(at 137.16 134.62)
(descr "Through hole pin header")
(tags "pin header")
(path /5AA1718D)
(fp_text reference P1 (at 0 5.1) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value CONN_01X02 (at 0 3.1) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.27 -1.27) (end 1.27 -3.81) (layer B.SilkS) (width 0.15))
(fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
(fp_line (start -1.75 1.75) (end -1.75 -4.3) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.75 1.75) (end 1.75 -4.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 -4.3) (end 1.75 -4.3) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
(fp_line (start -1.27 -1.27) (end -1.27 -3.81) (layer B.SilkS) (width 0.15))
(fp_line (start -1.27 -3.81) (end 1.27 -3.81) (layer B.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 1 /CLK))
(pad 2 thru_hole oval (at 0 -2.54) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 2 "Net-(P1-Pad2)"))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x02.wrl
(at (xyz 0 -0.05 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x08 (layer B.Cu) (tedit 5AA16C69) (tstamp 5AA26C80)
(at 137.16 111.76 180)
(descr "Through hole pin header")
(tags "pin header")
(path /5AA16BDE)
(fp_text reference P2 (at 0 5.1 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value CONN_01X08 (at 0 3.1 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.75 1.75) (end -1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.75 1.75) (end 1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 -19.55) (end 1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.27 -1.27) (end 1.27 -19.05) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -19.05) (end -1.27 -19.05) (layer B.SilkS) (width 0.15))
(fp_line (start -1.27 -19.05) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 3 "Net-(P2-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 4 "Net-(P2-Pad2)"))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 5 "Net-(P2-Pad3)"))
(pad 4 thru_hole oval (at 0 -7.62 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 6 "Net-(P2-Pad4)"))
(pad 5 thru_hole oval (at 0 -10.16 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 7 "Net-(P2-Pad5)"))
(pad 6 thru_hole oval (at 0 -12.7 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 8 "Net-(P2-Pad6)"))
(pad 7 thru_hole oval (at 0 -15.24 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 9 "Net-(P2-Pad7)"))
(pad 8 thru_hole oval (at 0 -17.78 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 10 "Net-(P2-Pad8)"))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x08.wrl
(at (xyz 0 -0.35 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x08 (layer B.Cu) (tedit 5AA16C76) (tstamp 5AA26C8C)
(at 137.16 91.44 180)
(descr "Through hole pin header")
(tags "pin header")
(path /5AA16D33)
(fp_text reference P3 (at 0 5.1 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value CONN_01X08 (at 0 3.1 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.75 1.75) (end -1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.75 1.75) (end 1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 -19.55) (end 1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.27 -1.27) (end 1.27 -19.05) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -19.05) (end -1.27 -19.05) (layer B.SilkS) (width 0.15))
(fp_line (start -1.27 -19.05) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 11 "Net-(P3-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 12 "Net-(P3-Pad2)"))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 13 "Net-(P3-Pad3)"))
(pad 4 thru_hole oval (at 0 -7.62 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 14 "Net-(P3-Pad4)"))
(pad 5 thru_hole oval (at 0 -10.16 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 15 "Net-(P3-Pad5)"))
(pad 6 thru_hole oval (at 0 -12.7 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 16 "Net-(P3-Pad6)"))
(pad 7 thru_hole oval (at 0 -15.24 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 17 "Net-(P3-Pad7)"))
(pad 8 thru_hole oval (at 0 -17.78 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 18 "Net-(P3-Pad8)"))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x08.wrl
(at (xyz 0 -0.35 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x02 (layer B.Cu) (tedit 5AA16CBF) (tstamp 5AA26C92)
(at 154.94 132.08 180)
(descr "Through hole pin header")
(tags "pin header")
(path /5AA1723C)
(fp_text reference P4 (at 0 5.1 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value CONN_01X02 (at 0 3.1 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.27 -1.27) (end 1.27 -3.81) (layer B.SilkS) (width 0.15))
(fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
(fp_line (start -1.75 1.75) (end -1.75 -4.3) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.75 1.75) (end 1.75 -4.3) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 -4.3) (end 1.75 -4.3) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
(fp_line (start -1.27 -1.27) (end -1.27 -3.81) (layer B.SilkS) (width 0.15))
(fp_line (start -1.27 -3.81) (end 1.27 -3.81) (layer B.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 19 VCC))
(pad 2 thru_hole rect (at 0 -2.54 180) (size 2.032 2.032) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 20 GND))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x02.wrl
(at (xyz 0 -0.05 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x08 (layer B.Cu) (tedit 5AA16CAC) (tstamp 5AA26C9E)
(at 154.94 111.76 180)
(descr "Through hole pin header")
(tags "pin header")
(path /5AA16DC2)
(fp_text reference P5 (at 0 5.1 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value CONN_01X08 (at 0 3.1 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.75 1.75) (end -1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.75 1.75) (end 1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 -19.55) (end 1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.27 -1.27) (end 1.27 -19.05) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -19.05) (end -1.27 -19.05) (layer B.SilkS) (width 0.15))
(fp_line (start -1.27 -19.05) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 21 "Net-(P5-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 22 "Net-(P5-Pad2)"))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 23 "Net-(P5-Pad3)"))
(pad 4 thru_hole oval (at 0 -7.62 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 24 "Net-(P5-Pad4)"))
(pad 5 thru_hole oval (at 0 -10.16 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 25 "Net-(P5-Pad5)"))
(pad 6 thru_hole oval (at 0 -12.7 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 26 "Net-(P5-Pad6)"))
(pad 7 thru_hole oval (at 0 -15.24 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 27 "Net-(P5-Pad7)"))
(pad 8 thru_hole oval (at 0 -17.78 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 28 "Net-(P5-Pad8)"))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x08.wrl
(at (xyz 0 -0.35 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x08 (layer B.Cu) (tedit 5AA16CA1) (tstamp 5AA26CAA)
(at 154.94 91.44 180)
(descr "Through hole pin header")
(tags "pin header")
(path /5AA16D73)
(fp_text reference P6 (at 0 5.1 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value CONN_01X08 (at 0 3.1 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -1.75 1.75) (end -1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.75 1.75) (end 1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 1.75) (end 1.75 1.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.75 -19.55) (end 1.75 -19.55) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.27 -1.27) (end 1.27 -19.05) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -19.05) (end -1.27 -19.05) (layer B.SilkS) (width 0.15))
(fp_line (start -1.27 -19.05) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start 1.55 1.55) (end 1.55 0) (layer B.SilkS) (width 0.15))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 0) (end -1.55 1.55) (layer B.SilkS) (width 0.15))
(fp_line (start -1.55 1.55) (end 1.55 1.55) (layer B.SilkS) (width 0.15))
(pad 1 thru_hole oval (at 0 0 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 29 "Net-(P6-Pad1)"))
(pad 2 thru_hole oval (at 0 -2.54 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 30 "Net-(P6-Pad2)"))
(pad 3 thru_hole oval (at 0 -5.08 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 31 "Net-(P6-Pad3)"))
(pad 4 thru_hole oval (at 0 -7.62 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 32 "Net-(P6-Pad4)"))
(pad 5 thru_hole oval (at 0 -10.16 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 33 "Net-(P6-Pad5)"))
(pad 6 thru_hole oval (at 0 -12.7 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 34 "Net-(P6-Pad6)"))
(pad 7 thru_hole oval (at 0 -15.24 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 35 "Net-(P6-Pad7)"))
(pad 8 thru_hole oval (at 0 -17.78 180) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask B.SilkS)
(net 36 "Net-(P6-Pad8)"))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x08.wrl
(at (xyz 0 -0.35 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Housings_SOIC:SOIC-20_7.5x12.8mm_Pitch1.27mm (layer F.Cu) (tedit 54130A77) (tstamp 5AA26CC2)
(at 146.05 121.92)
(descr "20-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5AA1662B)
(attr smd)
(fp_text reference U1 (at 0 -7.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS574 (at 0 7.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.95 -6.75) (end -5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.95 -6.75) (end 5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 -6.75) (end 5.95 -6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 6.75) (end 5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.875 -6.575) (end -3.875 -6.24) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 -6.575) (end 3.875 -6.24) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 6.575) (end 3.875 6.24) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 6.575) (end -3.875 6.24) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -6.575) (end 3.875 -6.575) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 6.575) (end 3.875 6.575) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -6.24) (end -5.675 -6.24) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -4.7 -5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 2 "Net-(P1-Pad2)"))
(pad 2 smd rect (at -4.7 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 3 "Net-(P2-Pad1)"))
(pad 3 smd rect (at -4.7 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 4 "Net-(P2-Pad2)"))
(pad 4 smd rect (at -4.7 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(P2-Pad3)"))
(pad 5 smd rect (at -4.7 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 6 "Net-(P2-Pad4)"))
(pad 6 smd rect (at -4.7 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 7 "Net-(P2-Pad5)"))
(pad 7 smd rect (at -4.7 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 8 "Net-(P2-Pad6)"))
(pad 8 smd rect (at -4.7 3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 9 "Net-(P2-Pad7)"))
(pad 9 smd rect (at -4.7 4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 10 "Net-(P2-Pad8)"))
(pad 10 smd rect (at -4.7 5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 20 GND))
(pad 11 smd rect (at 4.7 5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 1 /CLK))
(pad 12 smd rect (at 4.7 4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 28 "Net-(P5-Pad8)"))
(pad 13 smd rect (at 4.7 3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 27 "Net-(P5-Pad7)"))
(pad 14 smd rect (at 4.7 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 26 "Net-(P5-Pad6)"))
(pad 15 smd rect (at 4.7 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 25 "Net-(P5-Pad5)"))
(pad 16 smd rect (at 4.7 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 24 "Net-(P5-Pad4)"))
(pad 17 smd rect (at 4.7 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 23 "Net-(P5-Pad3)"))
(pad 18 smd rect (at 4.7 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 22 "Net-(P5-Pad2)"))
(pad 19 smd rect (at 4.7 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 21 "Net-(P5-Pad1)"))
(pad 20 smd rect (at 4.7 -5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 19 VCC))
(model Housings_SOIC.3dshapes/SOIC-20_7.5x12.8mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_SOIC:SOIC-20_7.5x12.8mm_Pitch1.27mm (layer F.Cu) (tedit 54130A77) (tstamp 5AA26CDA)
(at 146.05 100.33)
(descr "20-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5AA16784)
(attr smd)
(fp_text reference U2 (at 0 -7.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 74LS574 (at 0 7.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.95 -6.75) (end -5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.95 -6.75) (end 5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 -6.75) (end 5.95 -6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 6.75) (end 5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.875 -6.575) (end -3.875 -6.24) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 -6.575) (end 3.875 -6.24) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 6.575) (end 3.875 6.24) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 6.575) (end -3.875 6.24) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -6.575) (end 3.875 -6.575) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 6.575) (end 3.875 6.575) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -6.24) (end -5.675 -6.24) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -4.7 -5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 2 "Net-(P1-Pad2)"))
(pad 2 smd rect (at -4.7 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 11 "Net-(P3-Pad1)"))
(pad 3 smd rect (at -4.7 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(P3-Pad2)"))
(pad 4 smd rect (at -4.7 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 13 "Net-(P3-Pad3)"))
(pad 5 smd rect (at -4.7 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 14 "Net-(P3-Pad4)"))
(pad 6 smd rect (at -4.7 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 15 "Net-(P3-Pad5)"))
(pad 7 smd rect (at -4.7 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 16 "Net-(P3-Pad6)"))
(pad 8 smd rect (at -4.7 3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 17 "Net-(P3-Pad7)"))
(pad 9 smd rect (at -4.7 4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 18 "Net-(P3-Pad8)"))
(pad 10 smd rect (at -4.7 5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 20 GND))
(pad 11 smd rect (at 4.7 5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 1 /CLK))
(pad 12 smd rect (at 4.7 4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 36 "Net-(P6-Pad8)"))
(pad 13 smd rect (at 4.7 3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 35 "Net-(P6-Pad7)"))
(pad 14 smd rect (at 4.7 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 34 "Net-(P6-Pad6)"))
(pad 15 smd rect (at 4.7 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 33 "Net-(P6-Pad5)"))
(pad 16 smd rect (at 4.7 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 32 "Net-(P6-Pad4)"))
(pad 17 smd rect (at 4.7 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 "Net-(P6-Pad3)"))
(pad 18 smd rect (at 4.7 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 30 "Net-(P6-Pad2)"))
(pad 19 smd rect (at 4.7 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 29 "Net-(P6-Pad1)"))
(pad 20 smd rect (at 4.7 -5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
(net 19 VCC))
(model Housings_SOIC.3dshapes/SOIC-20_7.5x12.8mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(segment (start 150.75 106.045) (end 150.75 106.595) (width 0.25) (layer F.Cu) (net 1))
(segment (start 150.75 106.595) (end 148.468764 108.876236) (width 0.25) (layer F.Cu) (net 1))
(segment (start 148.468764 127.071788) (end 149.031976 127.635) (width 0.25) (layer F.Cu) (net 1))
(segment (start 148.468764 108.876236) (end 148.468764 127.071788) (width 0.25) (layer F.Cu) (net 1))
(segment (start 149.031976 127.635) (end 150.75 127.635) (width 0.25) (layer F.Cu) (net 1))
(segment (start 137.16 134.62) (end 144.315 134.62) (width 0.25) (layer F.Cu) (net 1))
(segment (start 144.315 134.62) (end 150.75 128.185) (width 0.25) (layer F.Cu) (net 1))
(segment (start 150.75 128.185) (end 150.75 127.635) (width 0.25) (layer F.Cu) (net 1))
(segment (start 141.35 116.205) (end 145.737132 116.205) (width 0.25) (layer F.Cu) (net 2))
(segment (start 145.737132 116.205) (end 145.737132 128.405841) (width 0.25) (layer F.Cu) (net 2))
(segment (start 145.737132 128.405841) (end 142.062973 132.08) (width 0.25) (layer F.Cu) (net 2))
(segment (start 142.062973 132.08) (end 138.59684 132.08) (width 0.25) (layer F.Cu) (net 2))
(segment (start 138.59684 132.08) (end 137.16 132.08) (width 0.25) (layer F.Cu) (net 2))
(segment (start 141.35 94.615) (end 142.025 94.615) (width 0.25) (layer F.Cu) (net 2))
(segment (start 142.025 94.615) (end 145.040833 97.630833) (width 0.25) (layer F.Cu) (net 2))
(segment (start 145.040833 97.630833) (end 145.040833 111.964167) (width 0.25) (layer F.Cu) (net 2))
(segment (start 145.040833 111.964167) (end 141.35 115.655) (width 0.25) (layer F.Cu) (net 2))
(segment (start 141.35 115.655) (end 141.35 116.205) (width 0.25) (layer F.Cu) (net 2))
(segment (start 141.35 117.475) (end 140.675 117.475) (width 0.25) (layer F.Cu) (net 3))
(segment (start 140.675 117.475) (end 139.322822 116.122822) (width 0.25) (layer F.Cu) (net 3))
(segment (start 139.322822 116.122822) (end 139.322822 113.770422) (width 0.25) (layer F.Cu) (net 3))
(segment (start 139.322822 113.770422) (end 137.3124 111.76) (width 0.25) (layer F.Cu) (net 3))
(segment (start 137.3124 111.76) (end 137.16 111.76) (width 0.25) (layer F.Cu) (net 3))
(segment (start 141.35 118.745) (end 140.675 118.745) (width 0.25) (layer F.Cu) (net 4))
(segment (start 140.675 118.745) (end 139.076459 117.146459) (width 0.25) (layer F.Cu) (net 4))
(segment (start 139.076459 117.146459) (end 139.076459 116.627868) (width 0.25) (layer F.Cu) (net 4))
(segment (start 139.076459 116.627868) (end 137.16 114.711409) (width 0.25) (layer F.Cu) (net 4))
(segment (start 137.16 114.711409) (end 137.16 114.3) (width 0.25) (layer F.Cu) (net 4))
(segment (start 141.35 120.015) (end 140.4874 120.015) (width 0.25) (layer F.Cu) (net 5))
(segment (start 140.4874 120.015) (end 137.3124 116.84) (width 0.25) (layer F.Cu) (net 5))
(segment (start 137.3124 116.84) (end 137.16 116.84) (width 0.25) (layer F.Cu) (net 5))
(segment (start 141.35 121.285) (end 139.065 121.285) (width 0.25) (layer F.Cu) (net 6))
(segment (start 139.065 121.285) (end 138.426 120.646) (width 0.25) (layer F.Cu) (net 6))
(segment (start 138.426 120.646) (end 138.426 120.4936) (width 0.25) (layer F.Cu) (net 6))
(segment (start 138.426 120.4936) (end 137.3124 119.38) (width 0.25) (layer F.Cu) (net 6))
(segment (start 137.3124 119.38) (end 137.16 119.38) (width 0.25) (layer F.Cu) (net 6))
(segment (start 141.35 122.555) (end 137.795 122.555) (width 0.25) (layer F.Cu) (net 7))
(segment (start 137.795 122.555) (end 137.16 121.92) (width 0.25) (layer F.Cu) (net 7))
(segment (start 141.35 123.825) (end 137.795 123.825) (width 0.25) (layer F.Cu) (net 8))
(segment (start 137.795 123.825) (end 137.16 124.46) (width 0.25) (layer F.Cu) (net 8))
(segment (start 141.35 125.095) (end 139.065 125.095) (width 0.25) (layer F.Cu) (net 9))
(segment (start 139.065 125.095) (end 138.426 125.734) (width 0.25) (layer F.Cu) (net 9))
(segment (start 138.426 125.734) (end 138.426 125.8864) (width 0.25) (layer F.Cu) (net 9))
(segment (start 137.3124 127) (end 137.16 127) (width 0.25) (layer F.Cu) (net 9))
(segment (start 138.426 125.8864) (end 137.3124 127) (width 0.25) (layer F.Cu) (net 9))
(segment (start 141.35 126.365) (end 140.675 126.365) (width 0.25) (layer F.Cu) (net 10))
(segment (start 140.675 126.365) (end 137.5 129.54) (width 0.25) (layer F.Cu) (net 10))
(segment (start 137.5 129.54) (end 137.16 129.54) (width 0.25) (layer F.Cu) (net 10))
(segment (start 141.35 95.885) (end 140.675 95.885) (width 0.25) (layer F.Cu) (net 11))
(segment (start 140.675 95.885) (end 139.252432 94.462432) (width 0.25) (layer F.Cu) (net 11))
(segment (start 139.252432 94.462432) (end 139.252432 93.380032) (width 0.25) (layer F.Cu) (net 11))
(segment (start 139.252432 93.380032) (end 137.3124 91.44) (width 0.25) (layer F.Cu) (net 11))
(segment (start 137.3124 91.44) (end 137.16 91.44) (width 0.25) (layer F.Cu) (net 11))
(segment (start 141.35 97.155) (end 140.4874 97.155) (width 0.25) (layer F.Cu) (net 12))
(segment (start 140.4874 97.155) (end 137.3124 93.98) (width 0.25) (layer F.Cu) (net 12))
(segment (start 137.3124 93.98) (end 137.16 93.98) (width 0.25) (layer F.Cu) (net 12))
(segment (start 141.35 98.425) (end 139.065 98.425) (width 0.25) (layer F.Cu) (net 13))
(segment (start 139.065 98.425) (end 138.426 97.786) (width 0.25) (layer F.Cu) (net 13))
(segment (start 138.426 97.786) (end 138.426 97.6336) (width 0.25) (layer F.Cu) (net 13))
(segment (start 138.426 97.6336) (end 137.3124 96.52) (width 0.25) (layer F.Cu) (net 13))
(segment (start 137.3124 96.52) (end 137.16 96.52) (width 0.25) (layer F.Cu) (net 13))
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60
boards/register/register.pro Normal file
View File

@ -0,0 +1,60 @@
update=Do 08 Mär 2018 17:32:40 CET
version=1
last_client=kicad
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=microcontrollers
LibName13=dsp
LibName14=microchip
LibName15=analog_switches
LibName16=motorola
LibName17=texas
LibName18=intel
LibName19=audio
LibName20=interface
LibName21=digital-audio
LibName22=philips
LibName23=display
LibName24=cypress
LibName25=siliconi
LibName26=opto
LibName27=atmel
LibName28=contrib
LibName29=valves
[general]
version=1

211
boards/register/register.sch Normal file
View File

@ -0,0 +1,211 @@
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
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