Klemens Schölhorn dfd2d2ac9b Use new ise virtex-6 parser and set SYNTHESIS verilog constant

2018-06-05 16:10:42 +02:00

..

.gitignore

Add basic ise project with relative paths

2018-06-05 16:04:27 +02:00

ml507_ddr2_clock.v

Import clock definition files

2018-06-05 16:04:27 +02:00

ml507_dvi_clock.v

Import clock definition files

2018-06-05 16:04:27 +02:00

ml507_sys_clock.v

Import clock definition files

2018-06-05 16:04:27 +02:00

risc-v-workstation.xise

Use new ise virtex-6 parser and set SYNTHESIS verilog constant

2018-06-05 16:10:42 +02:00