94 lines
3.4 KiB
Verilog
94 lines
3.4 KiB
Verilog
////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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////////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor: Xilinx
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// \ \ \/ Version : 14.7
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// \ \ Application : xaw2verilog
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// / / Filename : ml507_ddr2_clock.v
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// /___/ /\ Timestamp : 05/10/2018 01:18:22
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// \ \ / \
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// \___\/\___\
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//
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//Command: xaw2verilog -intstyle /repos/master/riscv_test/ipcore_dir/ml507_ddr2_clock.xaw -st ml507_ddr2_clock.v
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//Design Name: ml507_ddr2_clock
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//Device: xc5vfx70t-1ff1136
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//
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// Module ml507_ddr2_clock
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// Generated by Xilinx Architecture Wizard
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// Written for synthesis tool: XST
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`timescale 1ns / 1ps
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module ml507_ddr2_clock(CLKIN_N_IN,
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CLKIN_P_IN,
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CLKDV_OUT,
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CLKIN_IBUFGDS_OUT,
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CLK0_OUT,
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CLK90_OUT,
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LOCKED_OUT);
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input CLKIN_N_IN;
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input CLKIN_P_IN;
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output CLKDV_OUT;
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output CLKIN_IBUFGDS_OUT;
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output CLK0_OUT;
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output CLK90_OUT;
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output LOCKED_OUT;
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wire CLKDV_BUF;
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wire CLKFB_IN;
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wire CLKIN_IBUFGDS;
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wire CLK0_BUF;
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wire CLK90_BUF;
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wire GND_BIT;
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wire [6:0] GND_BUS_7;
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wire [15:0] GND_BUS_16;
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assign GND_BIT = 0;
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assign GND_BUS_7 = 7'b0000000;
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assign GND_BUS_16 = 16'b0000000000000000;
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assign CLKIN_IBUFGDS_OUT = CLKIN_IBUFGDS;
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assign CLK0_OUT = CLKFB_IN;
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BUFG CLKDV_BUFG_INST (.I(CLKDV_BUF),
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.O(CLKDV_OUT));
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IBUFGDS CLKIN_IBUFGDS_INST (.I(CLKIN_P_IN),
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.IB(CLKIN_N_IN),
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.O(CLKIN_IBUFGDS));
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BUFG CLK0_BUFG_INST (.I(CLK0_BUF),
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.O(CLKFB_IN));
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BUFG CLK90_BUFG_INST (.I(CLK90_BUF),
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.O(CLK90_OUT));
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DCM_ADV #( .CLK_FEEDBACK("1X"), .CLKDV_DIVIDE(2.0), .CLKFX_DIVIDE(1),
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.CLKFX_MULTIPLY(4), .CLKIN_DIVIDE_BY_2("FALSE"), .CLKIN_PERIOD(5.000),
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.CLKOUT_PHASE_SHIFT("NONE"), .DCM_AUTOCALIBRATION("TRUE"),
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.DCM_PERFORMANCE_MODE("MAX_SPEED"),
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.DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), .DFS_FREQUENCY_MODE("HIGH"),
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.DLL_FREQUENCY_MODE("HIGH"), .DUTY_CYCLE_CORRECTION("TRUE"),
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.FACTORY_JF(16'hF0F0), .PHASE_SHIFT(0), .STARTUP_WAIT("FALSE"),
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.SIM_DEVICE("VIRTEX5") ) DCM_ADV_INST (.CLKFB(CLKFB_IN),
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.CLKIN(CLKIN_IBUFGDS),
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.DADDR(GND_BUS_7[6:0]),
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.DCLK(GND_BIT),
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.DEN(GND_BIT),
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.DI(GND_BUS_16[15:0]),
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.DWE(GND_BIT),
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.PSCLK(GND_BIT),
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.PSEN(GND_BIT),
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.PSINCDEC(GND_BIT),
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.RST(GND_BIT),
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.CLKDV(CLKDV_BUF),
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.CLKFX(),
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.CLKFX180(),
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.CLK0(CLK0_BUF),
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.CLK2X(),
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.CLK2X180(),
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.CLK90(CLK90_BUF),
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.CLK180(),
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.CLK270(),
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.DO(),
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.DRDY(),
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.LOCKED(LOCKED_OUT),
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.PSDONE());
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endmodule
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