5 Commits

Include renames

Author	SHA1	Message	Date
klemens	ce76d77699	Add missing module to the ISE project and ignore generated MIG-Core	2018-06-05 17:15:48 +02:00
klemens	dfd2d2ac9b	Use new ise virtex-6 parser and set SYNTHESIS verilog constant	2018-06-05 16:10:42 +02:00
klemens	fbab58fa13	Add constraint files to the ise project	2018-06-05 16:04:27 +02:00
klemens	f9b72609f1	Import clock definition files	2018-06-05 16:04:27 +02:00
klemens	55cd91d4da	Add basic ise project with relative paths	2018-06-05 16:04:27 +02:00