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Add missing module to the ISE project and ignore generated MIG-Core

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This commit is contained in:
Klemens Schölhorn
2018-06-05 17:15:48 +02:00
parent dfd2d2ac9b
commit ce76d77699
2 changed files with 25 additions and 27 deletions
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10
project/ise/.gitignore vendored
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@ -65,6 +65,7 @@ xlnx_auto_0_xdb/
xst/
_ngo/
_xmsgs/
/ipcore_dir/
# isim
/isim*
@ -75,12 +76,3 @@ xilinxsim.ini
# log files
*.log
# ip cores
/ipcore_dir/*.cgc
/ipcore_dir/*.cgp
/ipcore_dir/*.tcl
/ipcore_dir/*.vhd
/ipcore_dir/*flist.txt
/ipcore_dir/_xmsgs/
/ipcore_dir/tmp/