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Add ch7301c initialization to the main unit

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This commit is contained in:
Klemens Schölhorn 2017-11-23 04:29:45 +01:00
parent ea6b3418de
commit ce043d2805
6 changed files with 52 additions and 49 deletions
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34
dvi_test.xise
View File

@ -17,7 +17,7 @@
<files>
<file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="vga_test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
@ -31,19 +31,23 @@
</file>
<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="ipcore_dir/clock_source.xaw" xil_pn:type="FILE_XAW">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="init_ch7301c.ucf" xil_pn:type="FILE_UCF">
<file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="image_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
</files>
<properties>
@ -163,9 +167,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|init_ch7301c|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="init_ch7301c.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/init_ch7301c" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="main.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@ -225,7 +229,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="init_ch7301c" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@ -238,10 +242,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="init_ch7301c_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="init_ch7301c_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="init_ch7301c_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="init_ch7301c_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="main_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
@ -264,7 +268,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="init_ch7301c" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="main" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
@ -374,7 +378,7 @@
</properties>
<bindings>
<binding xil_pn:location="/init_ch7301c" xil_pn:name="init_ch7301c.ucf"/>
<binding xil_pn:location="/main" xil_pn:name="main.ucf"/>
</bindings>
<libraries/>

13
init_ch7301c.ucf
View File

@ -5,16 +5,3 @@ NET "reset" LOC = AJ6; # center switch
NET "i2c_scl" LOC = U27;
NET "i2c_sda" LOC = T29;
NET "dvi_reset" LOC = AK6;
NET "led(0)" LOC = H18;
NET "led(1)" LOC = L18;
NET "led(2)" LOC = G15;
NET "led(3)" LOC = AD26;
NET "led(4)" LOC = G16;
NET "led(5)" LOC = AD25;
NET "led(6)" LOC = AD24;
NET "led(7)" LOC = AE24;
NET "led_n" LOC = AF13;
NET "led_s" LOC = AG12;
NET "led_c" LOC = E8;

28
init_ch7301c.vhd
View File

@ -7,25 +7,19 @@ use ieee.numeric_std.all;
entity init_ch7301c is
generic (
input_clk: integer := 27_000_000;
input_clk: integer;
address: std_logic_vector(6 downto 0) := "1110110" -- 0x76
);
port (
clk: in std_logic;
reset: in std_logic;
finished: buffer std_logic;
error: buffer std_logic;
finished: out std_logic;
error: out std_logic;
i2c_scl: inout std_logic;
i2c_sda: inout std_logic;
-- tmp
dvi_reset: out std_logic;
led: out std_logic_vector(7 downto 0);
led_n: out std_logic;
led_s: out std_logic;
led_c: out std_logic
dvi_reset: out std_logic
);
end init_ch7301c;
@ -58,15 +52,11 @@ begin
sda => i2c_sda
);
led_n <= error;
led_s <= finished;
led_c <= reset;
main: process(clk, reset)
-- ch7301c needs some time (>2µs) to init its i2c port after reset
constant max_delay: integer := input_clk / 200_000; -- 5µs
variable delay: integer range 0 to max_delay := 0;
variable busy_count: integer range 0 to 10 := 0;
variable busy_count: integer range 0 to 12 := 0;
begin
if reset = '1' then
delay := 0;
@ -139,6 +129,14 @@ begin
i2c_data_in <= x"60";
when 10 =>
-- select register CM (clock mode)
i2c_data_in <= x"1C";
when 11 =>
-- enable singledual edge clocking mode
-- single: 01, dual: 00 (default)
i2c_data_in <= x"01";
when 12 =>
-- no more commands
i2c_execute <= '0';
finished <= '1';

5
main.ucf
View File

@ -1,4 +1,3 @@
# DVI-Encoder Interface
NET "dvi_d(0)" LOC = AB8;
NET "dvi_d(1)" LOC = AC8;
@ -18,6 +17,8 @@ NET "dvi_hsync" LOC = AM12;
NET "dvi_vsync" LOC = AM11;
NET "dvi_de" LOC = AE8;
NET "dvi_reset" LOC = AK6;
NET "i2c_scl" LOC = U27;
NET "i2c_sda" LOC = T29;
NET "clk" LOC = AH15;
NET "clk" PERIOD = 100 MHz HIGH 50%;
@ -27,4 +28,4 @@ NET "switch_center" LOC = AJ6;
NET "led0" LOC = H18;
NET "led1" LOC = L18;
NET "led2" LOC = G15;
NET "led4" LOC = G16;
NET "led4" LOC = G16;

17
main.vhd
View File

@ -18,6 +18,8 @@ entity main is
dvi_vsync: out std_logic;
dvi_de: out std_logic;
dvi_reset: out std_logic;
i2c_scl: inout std_logic;
i2c_sda: inout std_logic;
switch_center: in std_logic;
led0: out std_logic;
@ -36,6 +38,7 @@ architecture Behavioral of main is
signal vsync: std_logic;
signal de: std_logic;
begin
-- convert the 100MHz to a 48MHz pixel clock
clock_source: entity work.clock_source port map (
CLKIN_IN => clk,
CLKFX_OUT => clk_vga
@ -48,6 +51,18 @@ begin
I => clk_vga
);
ch7301c: entity work.init_ch7301c generic map (
input_clk => 48_000_000
) port map (
clk => clk_vga,
reset => switch_center,
finished => open,
error => open,
i2c_scl => i2c_scl,
i2c_sda => i2c_sda,
dvi_reset => dvi_reset
);
vga_sync: entity work.vga port map (
clk => clk_vga,
--x, y (static color for now)
@ -67,6 +82,4 @@ begin
led1 <= dvi_clk;
led2 <= hsync;
led4 <= vsync;
dvi_reset <= not switch_center;
end Behavioral;

4
vga.vhd
View File

@ -24,8 +24,8 @@ architecture behavioral of vga is
signal vcount: std_logic_vector(9 downto 0) := (others => '0');
signal data_enabled: std_logic;
begin
--dvi_clk <= clk;
dvi_clk <= second_batch;
dvi_clk <= clk;
--dvi_clk <= second_batch;
dvi_de <= data_enabled;
data_enabled <= '1' when hcount < 640 and vcount < 480 else