86 lines
2.0 KiB
VHDL
86 lines
2.0 KiB
VHDL
library ieee;
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library unisim;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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-- Xilinx primitives (OBUFDS)
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use unisim.VComponents.all;
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entity main is
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port (
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clk: in std_logic;
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dvi_d: out std_logic_vector(11 downto 0);
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dvi_clk_p: out std_logic;
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dvi_clk_n: out std_logic;
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dvi_hsync: out std_logic;
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dvi_vsync: out std_logic;
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dvi_de: out std_logic;
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dvi_reset: out std_logic;
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i2c_scl: inout std_logic;
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i2c_sda: inout std_logic;
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switch_center: in std_logic;
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led0: out std_logic;
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led1: out std_logic;
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led2: out std_logic;
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led4: out std_logic
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);
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end main;
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architecture Behavioral of main is
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signal clk_vga: std_logic;
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signal pixel_rgb: std_logic_vector(23 downto 0) := "111111110000000011111111";
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signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds
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-- tmp
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signal hsync: std_logic;
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signal vsync: std_logic;
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signal de: std_logic;
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begin
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-- convert the 100MHz to a 48MHz pixel clock
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clock_source: entity work.clock_source port map (
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CLKIN_IN => clk,
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CLKFX_OUT => clk_vga
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);
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dvi_clk_ds: OBUFDS
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port map(
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O => dvi_clk_p,
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OB => dvi_clk_n,
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I => clk_vga
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);
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ch7301c: entity work.init_ch7301c generic map (
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input_clk => 48_000_000
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) port map (
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clk => clk_vga,
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reset => switch_center,
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finished => open,
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error => open,
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i2c_scl => i2c_scl,
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i2c_sda => i2c_sda,
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dvi_reset => dvi_reset
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);
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vga_sync: entity work.vga port map (
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clk => clk_vga,
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--x, y (static color for now)
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pixel_rgb => pixel_rgb,
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dvi_d => dvi_d,
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dvi_clk => dvi_clk,
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dvi_hsync => hsync,
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dvi_vsync => vsync,
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dvi_de => de
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);
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dvi_hsync <= hsync;
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dvi_vsync <= vsync;
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dvi_de <= de;
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led0 <= switch_center;
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led1 <= dvi_clk;
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led2 <= hsync;
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led4 <= vsync;
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end Behavioral;
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