Enable writing to the terminal buffer on second port

This adds an explicit terminal_buffer entity to help with the blockram
inference. Both read and write are completely independent, although they
run with the same clock for now.

dvi_test.xise

@@ -17,7 +17,7 @@
   <files>
     <file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="vga_test.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
@@ -27,34 +27,38 @@
     </file>
     <file xil_pn:name="i2c_master.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="ipcore_dir/clock_source.xaw" xil_pn:type="FILE_XAW">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="106"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="init_ch7301c.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="112"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="main.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="keyboard.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="153"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ps2.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="154"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="font_rom.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="155"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+    </file>
+    <file xil_pn:name="terminal_buffer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="156"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
   </files>
 

font_rom.vhd

@@ -13,7 +13,8 @@ entity font_rom is
     );
     port (
         clk: in std_logic;
-        x, y: in std_logic_vector(9 downto 0);
+        x: in std_logic_vector(9 downto 0);
+        y: in std_logic_vector(8 downto 0);
 
         rgb: out std_logic_vector(23 downto 0)
     );
@@ -40,14 +41,6 @@ architecture logic of font_rom is
 
     constant font: rom_type := read_font("font.hex");
 
-    type framebuffer_type is array(0 to 59, 0 to 79) of std_logic_vector(7 downto 0);
-    constant framebuffer: framebuffer_type := (
-        0 => (x"48", x"61", x"6C", x"6c", x"6f", others => x"00"),
-        1 to 59 => (others => x"00")
-    );
-
-    signal char_x: integer range 0 to 79;
-    signal char_y: integer range 0 to 59;
     signal current_char: std_logic_vector(7 downto 0);
 
     signal current_glyph: std_logic_vector(63 downto 0);
@@ -56,17 +49,53 @@ architecture logic of font_rom is
     constant glyph_pos_length: integer := 2;
     type glyph_pos_type is array(1 to glyph_pos_length) of integer range 0 to 63;
     signal glyph_pos: glyph_pos_type;
+
+    signal write_x: unsigned(6 downto 0);
+    signal write_y: unsigned(5 downto 0);
+    signal write_value: std_logic_vector(7 downto 0);
+
+    signal ra: std_logic_vector(12 downto 0);
+    signal wa: std_logic_vector(12 downto 0);
 begin
 
-    char_x <= to_integer(unsigned(x(9 downto 3)));
+    ra <= x(9 downto 3) & y(8 downto 3);
-    char_y <= to_integer(unsigned(y(9 downto 3)));
+    wa <= std_logic_vector(write_x) & std_logic_vector(write_y);
 
+    write_value <= "0" & std_logic_vector(write_x + 32);
+
+    cycle_write_location:
     process(clk)
+        constant max_delay: integer := 2000000;
+        variable delay: integer range 0 to max_delay;
     begin
         if rising_edge(clk) then
-            current_char <= framebuffer(char_y, char_x);
+            if delay = max_delay then
+                delay := 0;
+
+                if write_x = 79 then
+                    write_x <= (others => '0');
+                    if write_y = 59 then
+                        write_y <= (others => '0');
+                    else
+                        write_y <= write_y + 1;
                     end if;
-    end process;
+                else
+                    write_x <= write_x + 1;
+                end if;
+            else
+                delay := delay + 1;
+            end if;
+        end if;
+    end process cycle_write_location;
+
+    terminal_buffer: entity work.terminal_buffer port map (
+        clk => clk,
+        ra => ra,
+        do => current_char,
+        we => '1',
+        wa => wa,
+        di => write_value
+    );
 
     process(clk)
         variable current_glyph_pos: integer range 0 to 127;

main.vhd

@@ -41,7 +41,7 @@ end main;
 architecture Behavioral of main is
     signal clk_vga: std_logic;
     signal image_x: std_logic_vector(9 downto 0);
-    signal image_y: std_logic_vector(9 downto 0);
+    signal image_y: std_logic_vector(8 downto 0);
     signal pixel_rgb: std_logic_vector(23 downto 0);
     signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds
     -- tmp

terminal_buffer.vhd

@@ -0,0 +1,37 @@
+library ieee;
+
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity terminal_buffer is
+    port (
+        clk: in std_logic;
+        we: in std_logic;
+        wa: in std_logic_vector(12 downto 0);
+        ra: in std_logic_vector(12 downto 0);
+        di: in std_logic_vector(7 downto 0);
+        do: out std_logic_vector(7 downto 0)
+    );
+end terminal_buffer;
+
+architecture syn of terminal_buffer is
+    type ram_type is array((2**13 - 1) downto 0) of std_logic_vector(7 downto 0);
+    signal RAM: ram_type;
+    signal read_a: std_logic_vector(ra'range);
+begin
+
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            if we = '1' then
+                RAM(to_integer(unsigned(wa))) <= di;
+            end if;
+
+            read_a <= ra;
+        end if;
+    end process;
+
+    do <= RAM(to_integer(unsigned(read_a)));
+
+end syn;

vga.vhd

@@ -7,7 +7,8 @@ entity vga is
     port(
         clk: in std_logic;
 
-        x, y: out std_logic_vector(9 downto 0);
+        x: out std_logic_vector(9 downto 0);
+        y: out std_logic_vector(8 downto 0);
         pixel_rgb: in std_logic_vector(23 downto 0);
 
         dvi_d: out std_logic_vector(11 downto 0);
@@ -21,7 +22,7 @@ end vga;
 architecture behavioral of vga is
     signal second_batch: std_logic := '0';
     signal hcount: std_logic_vector(9 downto 0) := (others => '0');
-    signal vcount: std_logic_vector(9 downto 0) := (others => '0');
+    signal vcount: std_logic_vector(8 downto 0) := (others => '0');
     signal data_enabled: std_logic;
 begin
     dvi_clk <= clk;
@@ -37,7 +38,7 @@ begin
                  '1';
     
     x <= hcount when data_enabled = '1' and hcount < 640 else std_logic_vector(to_unsigned(639, 10));
-    y <= vcount when data_enabled = '1' and vcount < 480 else std_logic_vector(to_unsigned(479, 10));
+    y <= vcount when data_enabled = '1' and vcount < 480 else std_logic_vector(to_unsigned(479, 9));
     
     data_output: process(clk)
     begin