130 lines
3.6 KiB
VHDL
130 lines
3.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_unsigned.all;
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use ieee.numeric_std.all;
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use std.textio.all;
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use ieee.std_logic_textio.all;
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entity font_rom is
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generic (
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input_clk: integer
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);
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port (
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clk: in std_logic;
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x: in std_logic_vector(9 downto 0);
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y: in std_logic_vector(8 downto 0);
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rgb: out std_logic_vector(23 downto 0)
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);
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end font_rom;
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architecture logic of font_rom is
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type rom_type is array(0 to 127) of std_logic_vector(63 downto 0);
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impure function read_font(filename: in string) return rom_type is
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file rom_file: text is in filename;
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variable rom_line: line;
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variable rom: rom_type;
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begin
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-- skip comment in first line
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readline(rom_file, rom_line);
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for i in rom_type'range loop
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readline(rom_file, rom_line);
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hread(rom_line, rom(i));
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end loop;
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return rom;
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end function;
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constant font: rom_type := read_font("font.hex");
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signal current_char: std_logic_vector(7 downto 0);
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signal current_glyph: std_logic_vector(63 downto 0);
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-- delay by 2 cycles to match the delay of x/y -> rgb
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constant glyph_pos_length: integer := 2;
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type glyph_pos_type is array(1 to glyph_pos_length) of integer range 0 to 63;
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signal glyph_pos: glyph_pos_type;
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signal write_x: unsigned(6 downto 0);
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signal write_y: unsigned(5 downto 0);
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signal write_value: std_logic_vector(7 downto 0);
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signal ra: std_logic_vector(12 downto 0);
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signal wa: std_logic_vector(12 downto 0);
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begin
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ra <= x(9 downto 3) & y(8 downto 3);
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wa <= std_logic_vector(write_x) & std_logic_vector(write_y);
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write_value <= "0" & std_logic_vector(write_x + 32);
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cycle_write_location:
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process(clk)
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constant max_delay: integer := 2000000;
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variable delay: integer range 0 to max_delay;
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begin
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if rising_edge(clk) then
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if delay = max_delay then
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delay := 0;
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if write_x = 79 then
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write_x <= (others => '0');
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if write_y = 59 then
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write_y <= (others => '0');
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else
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write_y <= write_y + 1;
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end if;
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else
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write_x <= write_x + 1;
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end if;
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else
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delay := delay + 1;
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end if;
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end if;
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end process cycle_write_location;
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terminal_buffer: entity work.terminal_buffer port map (
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clk => clk,
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ra => ra,
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do => current_char,
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we => '1',
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wa => wa,
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di => write_value
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);
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process(clk)
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variable current_glyph_pos: integer range 0 to 127;
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begin
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if rising_edge(clk) then
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current_glyph_pos := to_integer(unsigned(current_char));
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current_glyph <= font(current_glyph_pos);
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end if;
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end process;
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delay_glyph_pos:
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process(clk)
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variable combined: std_logic_vector(5 downto 0);
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begin
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if rising_edge(clk) then
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combined := y(2 downto 0) & x(2 downto 0);
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glyph_pos(glyph_pos_length) <= to_integer(unsigned(combined));
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-- move all elements one index down
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for i in 1 to glyph_pos_length - 1 loop
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glyph_pos(i) <= glyph_pos(i + 1);
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end loop;
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end if;
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end process delay_glyph_pos;
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-- actually currently BRG
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rgb <=
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"111111111111111111111111" when current_glyph(glyph_pos(1)) = '1' else
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"000000000000000000000000";
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end logic;
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