Add basic example image generator

This commit is contained in:
Klemens Schölhorn 2017-11-23 04:32:27 +01:00
parent ce043d2805
commit 25130c1867
3 changed files with 107 additions and 5 deletions

82
image_generator.vhd Normal file
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@ -0,0 +1,82 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity image_generator is
generic (
input_clk: integer
);
port (
clk: in std_logic;
x, y: in std_logic_vector(9 downto 0);
ctrl_up: in std_logic;
ctrl_down: in std_logic;
rgb: out std_logic_vector(23 downto 0)
);
end image_generator;
architecture logic of image_generator is
type glyph is array(0 to 7) of std_logic_vector(7 downto 0);
constant emoji_grin: glyph := (
"00111100",
"01000010",
"10101001",
"10101001",
"10000101",
"10111001",
"01000010",
"00111100"
);
signal glyph_x: integer range 0 to 7;
signal glyph_y: integer range 0 to 7;
signal color: std_logic_vector(23 downto 0);
signal color_index: integer range 0 to 2;
begin
glyph_x <= to_integer(unsigned(x(4 downto 1)));
glyph_y <= to_integer(unsigned(y(4 downto 1)));
process(clk) is
variable last_up: std_logic;
variable last_down: std_logic;
constant debounce_max: integer := input_clk / 50; -- 20ms
variable debounce: integer range 0 to debounce_max := 0;
begin
if rising_edge(clk) then
if debounce = 0 then
if ctrl_up = '1' and last_up = '0' then
if color_index /= 2 then
color_index <= color_index + 1;
end if;
debounce := debounce_max;
end if;
last_up := ctrl_up;
if ctrl_down = '1' and last_down = '0' then
if color_index /= 0 then
color_index <= color_index - 1;
end if;
debounce := debounce_max;
end if;
last_down := ctrl_down;
else
debounce := debounce - 1;
end if;
end if;
end process;
with color_index select color <=
"111111111111111111111111" when 0,
"000000000000000011111111" when 1,
"000101001111111110110100" when 2;
-- actually currently BRG
rgb <=
color when x(4) = y(4) and emoji_grin(glyph_y)(glyph_x) = '1' else
"000000000000000000000000";
end logic;

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@ -24,6 +24,9 @@ NET "clk" LOC = AH15;
NET "clk" PERIOD = 100 MHz HIGH 50%; NET "clk" PERIOD = 100 MHz HIGH 50%;
NET "switch_center" LOC = AJ6; NET "switch_center" LOC = AJ6;
NET "rotary_up" LOC = AH30;
NET "rotary_down" LOC = AG30;
NET "rotary_push" LOC = AH29;
NET "led0" LOC = H18; NET "led0" LOC = H18;
NET "led1" LOC = L18; NET "led1" LOC = L18;

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@ -4,7 +4,7 @@ library unisim;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all; use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
-- Xilinx primitives (OBUFDS) -- Xilinx primitives (obufds)
use unisim.VComponents.all; use unisim.VComponents.all;
entity main is entity main is
@ -22,6 +22,10 @@ entity main is
i2c_sda: inout std_logic; i2c_sda: inout std_logic;
switch_center: in std_logic; switch_center: in std_logic;
rotary_up: in std_logic;
rotary_down: in std_logic;
rotary_push: in std_logic;
led0: out std_logic; led0: out std_logic;
led1: out std_logic; led1: out std_logic;
led2: out std_logic; led2: out std_logic;
@ -31,7 +35,9 @@ end main;
architecture Behavioral of main is architecture Behavioral of main is
signal clk_vga: std_logic; signal clk_vga: std_logic;
signal pixel_rgb: std_logic_vector(23 downto 0) := "111111110000000011111111"; signal image_x: std_logic_vector(9 downto 0);
signal image_y: std_logic_vector(9 downto 0);
signal pixel_rgb: std_logic_vector(23 downto 0);
signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds
-- tmp -- tmp
signal hsync: std_logic; signal hsync: std_logic;
@ -44,8 +50,7 @@ begin
CLKFX_OUT => clk_vga CLKFX_OUT => clk_vga
); );
dvi_clk_ds: OBUFDS dvi_clk_ds: obufds port map (
port map(
O => dvi_clk_p, O => dvi_clk_p,
OB => dvi_clk_n, OB => dvi_clk_n,
I => clk_vga I => clk_vga
@ -65,7 +70,8 @@ begin
vga_sync: entity work.vga port map ( vga_sync: entity work.vga port map (
clk => clk_vga, clk => clk_vga,
--x, y (static color for now) x => image_x,
y => image_y,
pixel_rgb => pixel_rgb, pixel_rgb => pixel_rgb,
dvi_d => dvi_d, dvi_d => dvi_d,
dvi_clk => dvi_clk, dvi_clk => dvi_clk,
@ -74,6 +80,17 @@ begin
dvi_de => de dvi_de => de
); );
image_generator_i: entity work.image_generator generic map (
input_clk => 48_000_000
) port map (
clk => clk_vga,
x => image_x,
y => image_y,
ctrl_up => rotary_up,
ctrl_down => rotary_down,
rgb => pixel_rgb
);
dvi_hsync <= hsync; dvi_hsync <= hsync;
dvi_vsync <= vsync; dvi_vsync <= vsync;
dvi_de <= de; dvi_de <= de;