commit 03659e9fb1da5323df08501b2f6871e9a4fd0ccf Author: Klemens Schölhorn Date: Mon Nov 13 02:29:11 2017 +0100 Import existing project for displaying images through DVI on the ml507 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..89f45bc --- /dev/null +++ b/.gitignore @@ -0,0 +1,86 @@ +# intermediate build files +*.bgn +*.bit +*.bld +*.cmd_log +*.drc +*.ll +*.lso +*.msd +*.msk +*.ncd +*.ngc +*.ngd +*.ngr +*.pad +*.par +*.pcf +*.prj +*.ptwx +*.rbb +*.rbd +*.stx +*.syr +*.twr +*.twx +*.unroutes +*.ut +*.xpi +*.xst +*_bitgen.xwbt +*_envsettings.html +*_map.map +*_map.mrp +*_map.ngm +*_map.xrpt +*_ngdbuild.xrpt +*_pad.csv +*_pad.txt +*_par.xrpt +*_summary.html +*_summary.xml +*_usage.xml +*_xst.xrpt + +# iMPACT generated files +_impactbatch.log +impact.xsl +impact_impact.xwbt +ise_impact.cmd +webtalk_impact.xml + +# Core Generator generated files +xaw2verilog.log + +# project-wide generated files +*.gise +par_usage_statistics.html +usage_statistics_webtalk.html +webtalk.log +webtalk_pn.xml + +# generated folders +iseconfig/ +xlnx_auto_0_xdb/ +xst/ +_ngo/ +_xmsgs/ + +# isim +/isim* +/fuse* +*.exe +*.wdb +xilinxsim.ini + +# log files +*.log + +# ip cores +/ipcore_dir/*.cgc +/ipcore_dir/*.cgp +/ipcore_dir/*.tcl +/ipcore_dir/*.vhd +/ipcore_dir/*flist.txt +/ipcore_dir/_xmsgs/ +/ipcore_dir/tmp/ diff --git a/clock_source.vhd b/clock_source.vhd new file mode 100644 index 0000000..25f48ca --- /dev/null +++ b/clock_source.vhd @@ -0,0 +1,108 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 14.7 +-- \ \ Application : xaw2vhdl +-- / / Filename : clock_source.vhd +-- /___/ /\ Timestamp : 11/13/2017 01:32:13 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: xaw2vhdl-intstyle /repos/master/dvi_test/ipcore_dir/clock_source.xaw -st clock_source.vhd +--Design Name: clock_source +--Device: xc5vfx70t-ff1136-3 +-- +-- Module clock_source +-- Generated by Xilinx Architecture Wizard +-- Written for synthesis tool: XST +-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.024 UI +-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.502 ns + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity clock_source is + port ( CLKIN_IN : in std_logic; + CLKFX_OUT : out std_logic; + CLKIN_IBUFG_OUT : out std_logic; + CLK0_OUT : out std_logic); +end clock_source; + +architecture BEHAVIORAL of clock_source is + signal CLKFB_IN : std_logic; + signal CLKFX_BUF : std_logic; + signal CLKIN_IBUFG : std_logic; + signal CLK0_BUF : std_logic; + signal GND_BIT : std_logic; + signal GND_BUS_7 : std_logic_vector (6 downto 0); + signal GND_BUS_16 : std_logic_vector (15 downto 0); +begin + GND_BIT <= '0'; + GND_BUS_7(6 downto 0) <= "0000000"; + GND_BUS_16(15 downto 0) <= "0000000000000000"; + CLKIN_IBUFG_OUT <= CLKIN_IBUFG; + CLK0_OUT <= CLKFB_IN; + CLKFX_BUFG_INST : BUFG + port map (I=>CLKFX_BUF, + O=>CLKFX_OUT); + + CLKIN_IBUFG_INST : IBUFG + port map (I=>CLKIN_IN, + O=>CLKIN_IBUFG); + + CLK0_BUFG_INST : BUFG + port map (I=>CLK0_BUF, + O=>CLKFB_IN); + + DCM_ADV_INST : DCM_ADV + generic map( CLK_FEEDBACK => "1X", + CLKDV_DIVIDE => 2.0, + CLKFX_DIVIDE => 25, + CLKFX_MULTIPLY => 12, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 10.000, + CLKOUT_PHASE_SHIFT => "NONE", + DCM_AUTOCALIBRATION => TRUE, + DCM_PERFORMANCE_MODE => "MAX_SPEED", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + DFS_FREQUENCY_MODE => "LOW", + DLL_FREQUENCY_MODE => "LOW", + DUTY_CYCLE_CORRECTION => TRUE, + FACTORY_JF => x"F0F0", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE, + SIM_DEVICE => "VIRTEX5") + port map (CLKFB=>CLKFB_IN, + CLKIN=>CLKIN_IBUFG, + DADDR(6 downto 0)=>GND_BUS_7(6 downto 0), + DCLK=>GND_BIT, + DEN=>GND_BIT, + DI(15 downto 0)=>GND_BUS_16(15 downto 0), + DWE=>GND_BIT, + PSCLK=>GND_BIT, + PSEN=>GND_BIT, + PSINCDEC=>GND_BIT, + RST=>GND_BIT, + CLKDV=>open, + CLKFX=>CLKFX_BUF, + CLKFX180=>open, + CLK0=>CLK0_BUF, + CLK2X=>open, + CLK2X180=>open, + CLK90=>open, + CLK180=>open, + CLK270=>open, + DO=>open, + DRDY=>open, + LOCKED=>open, + PSDONE=>open); + +end BEHAVIORAL; + + diff --git a/dvi_test.xise b/dvi_test.xise new file mode 100644 index 0000000..29b5525 --- /dev/null +++ b/dvi_test.xise @@ -0,0 +1,387 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/i2c_master.vhd b/i2c_master.vhd new file mode 100644 index 0000000..ef30a96 --- /dev/null +++ b/i2c_master.vhd @@ -0,0 +1,250 @@ +-- https://eewiki.net/pages/viewpage.action?pageId=10125324 +-- License unclear + +-------------------------------------------------------------------------------- +-- +-- FileName: i2c_master.vhd +-- Dependencies: none +-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version +-- +-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY +-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT +-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A +-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY +-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL +-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF +-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS +-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), +-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. +-- +-- Version History +-- Version 1.0 11/01/2012 Scott Larson +-- Initial Public Release +-- Version 2.0 06/20/2014 Scott Larson +-- Added ability to interface with different slaves in the same transaction +-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error +-- Corrected timing of when ack_error signal clears +-- Version 2.1 10/21/2014 Scott Larson +-- Replaced gated clock with clock enable +-- Adjusted timing of SCL during start and stop conditions +-- Version 2.2 02/05/2015 Scott Larson +-- Corrected small SDA glitch introduced in version 2.1 +-- +-------------------------------------------------------------------------------- + +LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_unsigned.all; + +ENTITY i2c_master IS + GENERIC( + input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz + bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz + PORT( + clk : IN STD_LOGIC; --system clock + reset_n : IN STD_LOGIC; --active low reset + ena : IN STD_LOGIC; --latch in command + addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave + rw : IN STD_LOGIC; --'0' is write, '1' is read + data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave + busy : OUT STD_LOGIC; --indicates transaction in progress + data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave + ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave + sda : INOUT STD_LOGIC; --serial data output of i2c bus + scl : INOUT STD_LOGIC); --serial clock output of i2c bus +END i2c_master; + +ARCHITECTURE logic OF i2c_master IS + CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl + TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states + SIGNAL state : machine; --state machine + SIGNAL data_clk : STD_LOGIC; --data clock for sda + SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock + SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl + SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output + SIGNAL sda_int : STD_LOGIC := '1'; --internal sda + SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output + SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write + SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave + SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave + SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction + SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl +BEGIN + + --generate the timing for the bus clock (scl_clk) and the data clock (data_clk) + PROCESS(clk, reset_n) + VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation + BEGIN + IF(reset_n = '0') THEN --reset asserted + stretch <= '0'; + count := 0; + ELSIF(clk'EVENT AND clk = '1') THEN + data_clk_prev <= data_clk; --store previous value of data clock + IF(count = divider*4-1) THEN --end of timing cycle + count := 0; --reset timer + ELSIF(stretch = '0') THEN --clock stretching from slave not detected + count := count + 1; --continue clock generation timing + END IF; + CASE count IS + WHEN 0 TO divider-1 => --first 1/4 cycle of clocking + scl_clk <= '0'; + data_clk <= '0'; + WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking + scl_clk <= '0'; + data_clk <= '1'; + WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking + scl_clk <= '1'; --release scl + IF(scl = '0') THEN --detect if slave is stretching clock + stretch <= '1'; + ELSE + stretch <= '0'; + END IF; + data_clk <= '1'; + WHEN OTHERS => --last 1/4 cycle of clocking + scl_clk <= '1'; + data_clk <= '0'; + END CASE; + END IF; + END PROCESS; + + --state machine and writing to sda during scl low (data_clk rising edge) + PROCESS(clk, reset_n) + BEGIN + IF(reset_n = '0') THEN --reset asserted + state <= ready; --return to initial state + busy <= '1'; --indicate not available + scl_ena <= '0'; --sets scl high impedance + sda_int <= '1'; --sets sda high impedance + ack_error <= '0'; --clear acknowledge error flag + bit_cnt <= 7; --restarts data bit counter + data_rd <= "00000000"; --clear data read port + ELSIF(clk'EVENT AND clk = '1') THEN + IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge + CASE state IS + WHEN ready => --idle state + IF(ena = '1') THEN --transaction requested + busy <= '1'; --flag busy + addr_rw <= addr & rw; --collect requested slave address and command + data_tx <= data_wr; --collect requested data to write + state <= start; --go to start bit + ELSE --remain idle + busy <= '0'; --unflag busy + state <= ready; --remain idle + END IF; + WHEN start => --start bit of transaction + busy <= '1'; --resume busy if continuous mode + sda_int <= addr_rw(bit_cnt); --set first address bit to bus + state <= command; --go to command + WHEN command => --address and command byte of transaction + IF(bit_cnt = 0) THEN --command transmit finished + sda_int <= '1'; --release sda for slave acknowledge + bit_cnt <= 7; --reset bit counter for "byte" states + state <= slv_ack1; --go to slave acknowledge (command) + ELSE --next clock cycle of command state + bit_cnt <= bit_cnt - 1; --keep track of transaction bits + sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus + state <= command; --continue with command + END IF; + WHEN slv_ack1 => --slave acknowledge bit (command) + IF(addr_rw(0) = '0') THEN --write command + sda_int <= data_tx(bit_cnt); --write first bit of data + state <= wr; --go to write byte + ELSE --read command + sda_int <= '1'; --release sda from incoming data + state <= rd; --go to read byte + END IF; + WHEN wr => --write byte of transaction + busy <= '1'; --resume busy if continuous mode + IF(bit_cnt = 0) THEN --write byte transmit finished + sda_int <= '1'; --release sda for slave acknowledge + bit_cnt <= 7; --reset bit counter for "byte" states + state <= slv_ack2; --go to slave acknowledge (write) + ELSE --next clock cycle of write state + bit_cnt <= bit_cnt - 1; --keep track of transaction bits + sda_int <= data_tx(bit_cnt-1); --write next bit to bus + state <= wr; --continue writing + END IF; + WHEN rd => --read byte of transaction + busy <= '1'; --resume busy if continuous mode + IF(bit_cnt = 0) THEN --read byte receive finished + IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address + sda_int <= '0'; --acknowledge the byte has been received + ELSE --stopping or continuing with a write + sda_int <= '1'; --send a no-acknowledge (before stop or repeated start) + END IF; + bit_cnt <= 7; --reset bit counter for "byte" states + data_rd <= data_rx; --output received data + state <= mstr_ack; --go to master acknowledge + ELSE --next clock cycle of read state + bit_cnt <= bit_cnt - 1; --keep track of transaction bits + state <= rd; --continue reading + END IF; + WHEN slv_ack2 => --slave acknowledge bit (write) + IF(ena = '1') THEN --continue transaction + busy <= '0'; --continue is accepted + addr_rw <= addr & rw; --collect requested slave address and command + data_tx <= data_wr; --collect requested data to write + IF(addr_rw = addr & rw) THEN --continue transaction with another write + sda_int <= data_wr(bit_cnt); --write first bit of data + state <= wr; --go to write byte + ELSE --continue transaction with a read or new slave + state <= start; --go to repeated start + END IF; + ELSE --complete transaction + state <= stop; --go to stop bit + END IF; + WHEN mstr_ack => --master acknowledge bit after a read + IF(ena = '1') THEN --continue transaction + busy <= '0'; --continue is accepted and data received is available on bus + addr_rw <= addr & rw; --collect requested slave address and command + data_tx <= data_wr; --collect requested data to write + IF(addr_rw = addr & rw) THEN --continue transaction with another read + sda_int <= '1'; --release sda from incoming data + state <= rd; --go to read byte + ELSE --continue transaction with a write or new slave + state <= start; --repeated start + END IF; + ELSE --complete transaction + state <= stop; --go to stop bit + END IF; + WHEN stop => --stop bit of transaction + busy <= '0'; --unflag busy + state <= ready; --go to idle state + END CASE; + ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge + CASE state IS + WHEN start => + IF(scl_ena = '0') THEN --starting new transaction + scl_ena <= '1'; --enable scl output + ack_error <= '0'; --reset acknowledge error output + END IF; + WHEN slv_ack1 => --receiving slave acknowledge (command) + IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge + ack_error <= '1'; --set error output if no-acknowledge + END IF; + WHEN rd => --receiving slave data + data_rx(bit_cnt) <= sda; --receive current slave data bit + WHEN slv_ack2 => --receiving slave acknowledge (write) + IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge + ack_error <= '1'; --set error output if no-acknowledge + END IF; + WHEN stop => + scl_ena <= '0'; --disable scl + WHEN OTHERS => + NULL; + END CASE; + END IF; + END IF; + END PROCESS; + + --set sda output + WITH state SELECT + sda_ena_n <= data_clk_prev WHEN start, --generate start condition + NOT data_clk_prev WHEN stop, --generate stop condition + sda_int WHEN OTHERS; --set to internal sda signal + + --set scl and sda outputs + scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z'; + sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z'; + +END logic; diff --git a/ipcore_dir/clock_source.xaw b/ipcore_dir/clock_source.xaw new file mode 100644 index 0000000..27c2b9a --- /dev/null +++ b/ipcore_dir/clock_source.xaw @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e +$8cx71=(zlzd"cnsugq+apnW}oxx"gcnpf[aou''%h`bmd_rmvvfc)ph}:7=;40/2100=7&<:9=6?9;02-456438:;>6?=4:37*2><9?-cJ=H?2:3[5>453;?:79<44958EWEO_@P:;6O]W[]LJI_XKHYHMIGAG^AOO4>b:CQS_YHFESTFDZ[ES]VMZHHFFCXI<94ASUY[JHKQVXNOB@IIF]SMKU6=2KY[WQ@NM[\V@UB\VFDKDM>2:CQS_YHFEST^HZNRFGW5==FZ^PTCCBV_WCOMAYCNZUFCIKn;@QPKFYPA]B:96OXZ^AOOGSA9VET_DIAALGe?DQ]WJF@NXH[YQG253=F_SUH@FLZFU[SA4YIGLNBX<=4AVX\GIMXG\^[YYQ[YQG`?DQ]WOFD[YW_E99BS_YWI[^o7LYU_R[MPMRHGE>0NBZG4:@VBB27>2IGG?9?5:AOO7^?3JF@>U?7049@HN?7=2IGGIXl;BNH@SYCA_COI85LLJDA<>EKCOHTEC;4CMIE\==DDBLS=5>6;BNHB]YE]Ol0OAEIX^@VBBYNFZ^h7NBDFY]GMSOCMl1H@FHW_LWOPLVKQ01H@FHW_NWW1>EKC@D:=6MCKHL\@LPNLLUIURBDEVK^XBMNLH@QEQOHF8>0HNCPPDPEKWKFFJOTABJJ3:FFJa=CMZAN[ROKJTQW57=CNZUM^H_ZEOAZ[HICM;1OEl5KLM]BJAYAP880HABPFSGRQ@HDQVGDHH<4DN68@WB^9<1OYYWPCXAOAZEHZ[OHXDAA3:FTA2=CW_KGYH64EYVFVKGKi2LJOYA]Y^HE1>@FDZO27KLPSNWQG@e@NFV_EEY]7;GMVPZUSZh1MCXZPUOKWWd=AG\^TZLBZE09J1>OE]OM37D@[ESLBH472Q;6<;R5:Y3>3[33hx|v>5kcl`8r`ttafd+=#>;;wjgh446495121`=3?=k<<0h4;50;395~U3k33>6495121`=3?=19=0zY6n:182>4h64;5968276e>>002<:5m8783>5<321q/j779;%0;><><,;31545+2`8;a>"?k320n8>50;3;>5<7s-=269h4$02973=#9803>6*>3;0g?!7e2180(7;57?!7>281/=l474:&2b?073-8;6;>4$33925=#"3?3?0(9655d9'0<<092.>=768;%71>3b<,<>1485+5485g>"203j774$7392<=#>:0=i6*95;4f?!012l1/:l494:&5b?b<,>?1=6*73;43?!>?2130(<<56:&13?303-896?l4$939<2.<;768;%55>=1<3`?=6=4+798:7>"0?32<7)99:958?l3d290/;5462:&43?>032c>?7>5$6:9=7=#?>03;65f4d83>!1?2080(:958698m2`=83.<477=;%54>=1<3`=o6=4+798:6>"0?32<76g8e;29 2>=1;1/;:477:9j3g<72-=364<4$659<2=215?54o2094?"0033976a<6;29 2>=1;10c>=50;&45$6:9=7=<4<3f?j6=4+798:6>=h=00;6)97:818 20=0>10c;l50;&45$6:9=7=?6=4=:183!1>2?20e;950;&45<#?102>6*8a;:4?>{e:o0;6?4?:1y'3<<5k2c=;7>5$6:9=7=#?h03;65`7383>!1?2080(:o58698yg5c29096=4?{%5:>7e:2.5<5s4?;6>64=3d937=#::08<6s|2d83>7}:=909h63=f;44?xu4k3:1>v3:0;1b?85c2?=0q~:9:1828232?=0(5>5669~w16=83;p1>j5739'<5<0:2wx884?:1y'<5<0:2wx?=4?:1y'<5<0:2wvb?o50;3xyk4e290:wp`=c;295~{i:m0;6{|l04?6=9rwe?<4?:0y~yx{GHJq8m7:6517`f0{GHKq;qMN_{|BC \ No newline at end of file diff --git a/main.ucf b/main.ucf new file mode 100644 index 0000000..13d8b64 --- /dev/null +++ b/main.ucf @@ -0,0 +1,30 @@ + +# DVI-Encoder Interface +NET "dvi_d(0)" LOC = AB8; +NET "dvi_d(1)" LOC = AC8; +NET "dvi_d(2)" LOC = AN12; +NET "dvi_d(3)" LOC = AP12; +NET "dvi_d(4)" LOC = AA9; +NET "dvi_d(5)" LOC = AA8; +NET "dvi_d(6)" LOC = AM13; +NET "dvi_d(7)" LOC = AN13; +NET "dvi_d(8)" LOC = AA10; +NET "dvi_d(9)" LOC = AB10; +NET "dvi_d(10)" LOC = AP14; +NET "dvi_d(11)" LOC = AN14; +NET "dvi_clk_p" LOC = AL11; +NET "dvi_clk_n" LOC = AL10; +NET "dvi_hsync" LOC = AM12; +NET "dvi_vsync" LOC = AM11; +NET "dvi_de" LOC = AE8; +NET "dvi_reset" LOC = AK6; + +NET "clk" LOC = AH15; +NET "clk" PERIOD = 100 MHz HIGH 50%; + +NET "switch_center" LOC = AJ6; + +NET "led0" LOC = H18; +NET "led1" LOC = L18; +NET "led2" LOC = G15; +NET "led4" LOC = G16; \ No newline at end of file diff --git a/main.vhd b/main.vhd new file mode 100644 index 0000000..97b5197 --- /dev/null +++ b/main.vhd @@ -0,0 +1,72 @@ +library ieee; +library unisim; + +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; +-- Xilinx primitives (OBUFDS) +use unisim.VComponents.all; + +entity main is + port ( + clk: in std_logic; + + dvi_d: out std_logic_vector(11 downto 0); + dvi_clk_p: out std_logic; + dvi_clk_n: out std_logic; + dvi_hsync: out std_logic; + dvi_vsync: out std_logic; + dvi_de: out std_logic; + dvi_reset: out std_logic; + + switch_center: in std_logic; + led0: out std_logic; + led1: out std_logic; + led2: out std_logic; + led4: out std_logic + ); +end main; + +architecture Behavioral of main is + signal clk_vga: std_logic; + signal pixel_rgb: std_logic_vector(23 downto 0) := "111111110000000011111111"; + signal dvi_clk: std_logic; -- connect vga_sync to dvi_clk_ds + -- tmp + signal hsync: std_logic; + signal vsync: std_logic; + signal de: std_logic; +begin + clock_source: entity work.clock_source port map ( + CLKIN_IN => clk, + CLKFX_OUT => clk_vga + ); + + dvi_clk_ds: OBUFDS + port map( + O => dvi_clk_p, + OB => dvi_clk_n, + I => clk_vga + ); + + vga_sync: entity work.vga port map ( + clk => clk_vga, + --x, y (static color for now) + pixel_rgb => pixel_rgb, + dvi_d => dvi_d, + dvi_clk => dvi_clk, + dvi_hsync => hsync, + dvi_vsync => vsync, + dvi_de => de + ); + + dvi_hsync <= hsync; + dvi_vsync <= vsync; + dvi_de <= de; + + led0 <= switch_center; + led1 <= dvi_clk; + led2 <= hsync; + led4 <= vsync; + + dvi_reset <= not switch_center; +end Behavioral; diff --git a/vga.vhd b/vga.vhd new file mode 100644 index 0000000..6917294 --- /dev/null +++ b/vga.vhd @@ -0,0 +1,80 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity vga is + port( + clk: in std_logic; + + x, y: out std_logic_vector(9 downto 0); + pixel_rgb: in std_logic_vector(23 downto 0); + + dvi_d: out std_logic_vector(11 downto 0); + dvi_clk: out std_logic; + dvi_hsync: out std_logic; + dvi_vsync: out std_logic; + dvi_de: out std_logic + ); +end vga; + +architecture behavioral of vga is + signal second_batch: std_logic := '0'; + signal hcount: std_logic_vector(9 downto 0) := (others => '0'); + signal vcount: std_logic_vector(9 downto 0) := (others => '0'); + signal data_enabled: std_logic; +begin + --dvi_clk <= clk; + dvi_clk <= second_batch; + dvi_de <= data_enabled; + + data_enabled <= '1' when hcount < 640 and vcount < 480 else + '0'; + + dvi_hsync <= '0' when 656 <= hcount and hcount <= 720 else + '1'; + dvi_vsync <= '0' when 483 <= vcount and vcount <= 487 else + '1'; + + x <= hcount when data_enabled = '1' and hcount < 640 else std_logic_vector(to_unsigned(639, 10)); + y <= vcount when data_enabled = '1' and vcount < 480 else std_logic_vector(to_unsigned(479, 10)); + + data_output: process(clk) + begin + if rising_edge(clk) then + if data_enabled = '1' then + if second_batch = '0' then + dvi_d <= pixel_rgb(11 downto 0); + else + dvi_d <= pixel_rgb(23 downto 12); + end if; + else + dvi_d <= (others => '0'); + end if; + + second_batch <= not second_batch; + end if; + end process data_output; + + hcounter: process(clk) + begin + if rising_edge(clk) and second_batch = '1' then + if hcount < 799 then + hcount <= hcount + 1; + else + hcount <= (others => '0'); + end if; + end if; + end process hcounter; + + vcounter: process(clk, hcount) + begin + if rising_edge(clk) and second_batch = '1' and hcount = 700 then + if vcount < 499 then + vcount <= vcount + 1; + else + vcount <= (others => '0'); + end if; + end if; + end process vcounter; +end behavioral; diff --git a/vga_test.vhd b/vga_test.vhd new file mode 100644 index 0000000..f429621 --- /dev/null +++ b/vga_test.vhd @@ -0,0 +1,104 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 01:47:34 11/01/2017 +-- Design Name: +-- Module Name: /repos/master/dvi_test/vga_test.vhd +-- Project Name: dvi_test +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: vga +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY vga_test IS +END vga_test; + +ARCHITECTURE behavior OF vga_test IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT vga + PORT( + clk : IN std_logic; + --x : OUT std_logic_vector(9 downto 0); + --y : OUT std_logic_vector(9 downto 0); + --pixel_rgb : IN std_logic_vector(23 downto 0); + dvi_d : OUT std_logic_vector(11 downto 0); + --dvi_clk : OUT std_logic; + dvi_clk_p : OUT std_logic; + dvi_clk_n : OUT std_logic; + dvi_hsync : OUT std_logic; + dvi_vsync : OUT std_logic; + dvi_de : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + --signal pixel_rgb : std_logic_vector(23 downto 0) := (others => '0'); + + --Outputs + --signal x : std_logic_vector(9 downto 0); + --signal y : std_logic_vector(9 downto 0); + signal dvi_d : std_logic_vector(11 downto 0); + --signal dvi_clk : std_logic; + signal dvi_clk_p : std_logic; + signal dvi_clk_n : std_logic; + signal dvi_hsync : std_logic; + signal dvi_vsync : std_logic; + signal dvi_de : std_logic; + + -- Clock period definitions + constant clk_period : time := 20834 ps; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: vga PORT MAP ( + clk => clk, + --x => x, + --y => y, + --pixel_rgb => pixel_rgb, + dvi_d => dvi_d, + --dvi_clk => dvi_clk, + dvi_clk_p => dvi_clk_p, + dvi_clk_n => dvi_clk_n, + dvi_hsync => dvi_hsync, + dvi_vsync => dvi_vsync, + dvi_de => dvi_de + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '0'; + wait for clk_period/2; + clk <= '1'; + wait for clk_period/2; + end process; + + --pixel_rgb <= "111111111111000000000001"; +END;