105 lines
2.8 KiB
VHDL
105 lines
2.8 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 01:47:34 11/01/2017
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-- Design Name:
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-- Module Name: /repos/master/dvi_test/vga_test.vhd
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-- Project Name: dvi_test
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: vga
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY vga_test IS
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END vga_test;
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ARCHITECTURE behavior OF vga_test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT vga
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PORT(
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clk : IN std_logic;
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--x : OUT std_logic_vector(9 downto 0);
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--y : OUT std_logic_vector(9 downto 0);
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--pixel_rgb : IN std_logic_vector(23 downto 0);
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dvi_d : OUT std_logic_vector(11 downto 0);
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--dvi_clk : OUT std_logic;
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dvi_clk_p : OUT std_logic;
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dvi_clk_n : OUT std_logic;
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dvi_hsync : OUT std_logic;
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dvi_vsync : OUT std_logic;
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dvi_de : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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--signal pixel_rgb : std_logic_vector(23 downto 0) := (others => '0');
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--Outputs
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--signal x : std_logic_vector(9 downto 0);
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--signal y : std_logic_vector(9 downto 0);
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signal dvi_d : std_logic_vector(11 downto 0);
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--signal dvi_clk : std_logic;
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signal dvi_clk_p : std_logic;
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signal dvi_clk_n : std_logic;
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signal dvi_hsync : std_logic;
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signal dvi_vsync : std_logic;
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signal dvi_de : std_logic;
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-- Clock period definitions
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constant clk_period : time := 20834 ps;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: vga PORT MAP (
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clk => clk,
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--x => x,
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--y => y,
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--pixel_rgb => pixel_rgb,
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dvi_d => dvi_d,
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--dvi_clk => dvi_clk,
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dvi_clk_p => dvi_clk_p,
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dvi_clk_n => dvi_clk_n,
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dvi_hsync => dvi_hsync,
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dvi_vsync => dvi_vsync,
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dvi_de => dvi_de
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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--pixel_rgb <= "111111111111000000000001";
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END;
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