251 lines
14 KiB
VHDL
251 lines
14 KiB
VHDL
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-- https://eewiki.net/pages/viewpage.action?pageId=10125324
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-- License unclear
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--------------------------------------------------------------------------------
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--
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-- FileName: i2c_master.vhd
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-- Dependencies: none
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-- Design Software: Quartus II 64-bit Version 13.1 Build 162 SJ Full Version
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--
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-- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY
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-- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
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-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
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-- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
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-- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
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-- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
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-- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
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-- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
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--
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-- Version History
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-- Version 1.0 11/01/2012 Scott Larson
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-- Initial Public Release
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-- Version 2.0 06/20/2014 Scott Larson
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-- Added ability to interface with different slaves in the same transaction
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-- Corrected ack_error bug where ack_error went 'Z' instead of '1' on error
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-- Corrected timing of when ack_error signal clears
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-- Version 2.1 10/21/2014 Scott Larson
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-- Replaced gated clock with clock enable
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-- Adjusted timing of SCL during start and stop conditions
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-- Version 2.2 02/05/2015 Scott Larson
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-- Corrected small SDA glitch introduced in version 2.1
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--
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_unsigned.all;
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ENTITY i2c_master IS
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GENERIC(
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input_clk : INTEGER := 50_000_000; --input clock speed from user logic in Hz
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bus_clk : INTEGER := 400_000); --speed the i2c bus (scl) will run at in Hz
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PORT(
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clk : IN STD_LOGIC; --system clock
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reset_n : IN STD_LOGIC; --active low reset
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ena : IN STD_LOGIC; --latch in command
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addr : IN STD_LOGIC_VECTOR(6 DOWNTO 0); --address of target slave
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rw : IN STD_LOGIC; --'0' is write, '1' is read
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data_wr : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --data to write to slave
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busy : OUT STD_LOGIC; --indicates transaction in progress
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data_rd : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --data read from slave
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ack_error : BUFFER STD_LOGIC; --flag if improper acknowledge from slave
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sda : INOUT STD_LOGIC; --serial data output of i2c bus
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scl : INOUT STD_LOGIC); --serial clock output of i2c bus
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END i2c_master;
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ARCHITECTURE logic OF i2c_master IS
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CONSTANT divider : INTEGER := (input_clk/bus_clk)/4; --number of clocks in 1/4 cycle of scl
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TYPE machine IS(ready, start, command, slv_ack1, wr, rd, slv_ack2, mstr_ack, stop); --needed states
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SIGNAL state : machine; --state machine
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SIGNAL data_clk : STD_LOGIC; --data clock for sda
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SIGNAL data_clk_prev : STD_LOGIC; --data clock during previous system clock
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SIGNAL scl_clk : STD_LOGIC; --constantly running internal scl
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SIGNAL scl_ena : STD_LOGIC := '0'; --enables internal scl to output
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SIGNAL sda_int : STD_LOGIC := '1'; --internal sda
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SIGNAL sda_ena_n : STD_LOGIC; --enables internal sda to output
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SIGNAL addr_rw : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in address and read/write
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SIGNAL data_tx : STD_LOGIC_VECTOR(7 DOWNTO 0); --latched in data to write to slave
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SIGNAL data_rx : STD_LOGIC_VECTOR(7 DOWNTO 0); --data received from slave
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SIGNAL bit_cnt : INTEGER RANGE 0 TO 7 := 7; --tracks bit number in transaction
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SIGNAL stretch : STD_LOGIC := '0'; --identifies if slave is stretching scl
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BEGIN
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--generate the timing for the bus clock (scl_clk) and the data clock (data_clk)
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PROCESS(clk, reset_n)
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VARIABLE count : INTEGER RANGE 0 TO divider*4; --timing for clock generation
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BEGIN
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IF(reset_n = '0') THEN --reset asserted
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stretch <= '0';
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count := 0;
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ELSIF(clk'EVENT AND clk = '1') THEN
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data_clk_prev <= data_clk; --store previous value of data clock
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IF(count = divider*4-1) THEN --end of timing cycle
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count := 0; --reset timer
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ELSIF(stretch = '0') THEN --clock stretching from slave not detected
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count := count + 1; --continue clock generation timing
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END IF;
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CASE count IS
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WHEN 0 TO divider-1 => --first 1/4 cycle of clocking
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scl_clk <= '0';
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data_clk <= '0';
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WHEN divider TO divider*2-1 => --second 1/4 cycle of clocking
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scl_clk <= '0';
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data_clk <= '1';
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WHEN divider*2 TO divider*3-1 => --third 1/4 cycle of clocking
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scl_clk <= '1'; --release scl
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IF(scl = '0') THEN --detect if slave is stretching clock
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stretch <= '1';
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ELSE
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stretch <= '0';
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END IF;
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data_clk <= '1';
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WHEN OTHERS => --last 1/4 cycle of clocking
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scl_clk <= '1';
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data_clk <= '0';
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END CASE;
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END IF;
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END PROCESS;
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--state machine and writing to sda during scl low (data_clk rising edge)
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PROCESS(clk, reset_n)
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BEGIN
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IF(reset_n = '0') THEN --reset asserted
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state <= ready; --return to initial state
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busy <= '1'; --indicate not available
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scl_ena <= '0'; --sets scl high impedance
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sda_int <= '1'; --sets sda high impedance
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ack_error <= '0'; --clear acknowledge error flag
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bit_cnt <= 7; --restarts data bit counter
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data_rd <= "00000000"; --clear data read port
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ELSIF(clk'EVENT AND clk = '1') THEN
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IF(data_clk = '1' AND data_clk_prev = '0') THEN --data clock rising edge
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CASE state IS
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WHEN ready => --idle state
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IF(ena = '1') THEN --transaction requested
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busy <= '1'; --flag busy
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addr_rw <= addr & rw; --collect requested slave address and command
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data_tx <= data_wr; --collect requested data to write
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state <= start; --go to start bit
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ELSE --remain idle
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busy <= '0'; --unflag busy
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state <= ready; --remain idle
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END IF;
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WHEN start => --start bit of transaction
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busy <= '1'; --resume busy if continuous mode
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sda_int <= addr_rw(bit_cnt); --set first address bit to bus
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state <= command; --go to command
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WHEN command => --address and command byte of transaction
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IF(bit_cnt = 0) THEN --command transmit finished
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sda_int <= '1'; --release sda for slave acknowledge
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bit_cnt <= 7; --reset bit counter for "byte" states
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state <= slv_ack1; --go to slave acknowledge (command)
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ELSE --next clock cycle of command state
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bit_cnt <= bit_cnt - 1; --keep track of transaction bits
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sda_int <= addr_rw(bit_cnt-1); --write address/command bit to bus
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state <= command; --continue with command
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END IF;
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WHEN slv_ack1 => --slave acknowledge bit (command)
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IF(addr_rw(0) = '0') THEN --write command
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sda_int <= data_tx(bit_cnt); --write first bit of data
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state <= wr; --go to write byte
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ELSE --read command
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sda_int <= '1'; --release sda from incoming data
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state <= rd; --go to read byte
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END IF;
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WHEN wr => --write byte of transaction
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busy <= '1'; --resume busy if continuous mode
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IF(bit_cnt = 0) THEN --write byte transmit finished
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sda_int <= '1'; --release sda for slave acknowledge
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bit_cnt <= 7; --reset bit counter for "byte" states
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state <= slv_ack2; --go to slave acknowledge (write)
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ELSE --next clock cycle of write state
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bit_cnt <= bit_cnt - 1; --keep track of transaction bits
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sda_int <= data_tx(bit_cnt-1); --write next bit to bus
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state <= wr; --continue writing
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END IF;
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WHEN rd => --read byte of transaction
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busy <= '1'; --resume busy if continuous mode
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IF(bit_cnt = 0) THEN --read byte receive finished
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IF(ena = '1' AND addr_rw = addr & rw) THEN --continuing with another read at same address
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sda_int <= '0'; --acknowledge the byte has been received
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ELSE --stopping or continuing with a write
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sda_int <= '1'; --send a no-acknowledge (before stop or repeated start)
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END IF;
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bit_cnt <= 7; --reset bit counter for "byte" states
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data_rd <= data_rx; --output received data
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state <= mstr_ack; --go to master acknowledge
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ELSE --next clock cycle of read state
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bit_cnt <= bit_cnt - 1; --keep track of transaction bits
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state <= rd; --continue reading
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END IF;
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WHEN slv_ack2 => --slave acknowledge bit (write)
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IF(ena = '1') THEN --continue transaction
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busy <= '0'; --continue is accepted
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addr_rw <= addr & rw; --collect requested slave address and command
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data_tx <= data_wr; --collect requested data to write
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IF(addr_rw = addr & rw) THEN --continue transaction with another write
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sda_int <= data_wr(bit_cnt); --write first bit of data
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state <= wr; --go to write byte
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ELSE --continue transaction with a read or new slave
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state <= start; --go to repeated start
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END IF;
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ELSE --complete transaction
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state <= stop; --go to stop bit
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END IF;
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WHEN mstr_ack => --master acknowledge bit after a read
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IF(ena = '1') THEN --continue transaction
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busy <= '0'; --continue is accepted and data received is available on bus
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addr_rw <= addr & rw; --collect requested slave address and command
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data_tx <= data_wr; --collect requested data to write
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IF(addr_rw = addr & rw) THEN --continue transaction with another read
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sda_int <= '1'; --release sda from incoming data
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state <= rd; --go to read byte
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ELSE --continue transaction with a write or new slave
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state <= start; --repeated start
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END IF;
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ELSE --complete transaction
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state <= stop; --go to stop bit
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END IF;
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WHEN stop => --stop bit of transaction
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busy <= '0'; --unflag busy
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state <= ready; --go to idle state
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END CASE;
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ELSIF(data_clk = '0' AND data_clk_prev = '1') THEN --data clock falling edge
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CASE state IS
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WHEN start =>
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IF(scl_ena = '0') THEN --starting new transaction
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scl_ena <= '1'; --enable scl output
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ack_error <= '0'; --reset acknowledge error output
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END IF;
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WHEN slv_ack1 => --receiving slave acknowledge (command)
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IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
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ack_error <= '1'; --set error output if no-acknowledge
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END IF;
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WHEN rd => --receiving slave data
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data_rx(bit_cnt) <= sda; --receive current slave data bit
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WHEN slv_ack2 => --receiving slave acknowledge (write)
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IF(sda /= '0' OR ack_error = '1') THEN --no-acknowledge or previous no-acknowledge
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ack_error <= '1'; --set error output if no-acknowledge
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END IF;
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WHEN stop =>
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scl_ena <= '0'; --disable scl
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WHEN OTHERS =>
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NULL;
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END CASE;
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END IF;
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END IF;
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END PROCESS;
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--set sda output
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WITH state SELECT
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sda_ena_n <= data_clk_prev WHEN start, --generate start condition
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NOT data_clk_prev WHEN stop, --generate stop condition
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sda_int WHEN OTHERS; --set to internal sda signal
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--set scl and sda outputs
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scl <= '0' WHEN (scl_ena = '1' AND scl_clk = '0') ELSE 'Z';
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sda <= '0' WHEN sda_ena_n = '0' ELSE 'Z';
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END logic;
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