109 lines
3.5 KiB
VHDL
109 lines
3.5 KiB
VHDL
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-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version : 14.7
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-- \ \ Application : xaw2vhdl
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-- / / Filename : clock_source.vhd
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-- /___/ /\ Timestamp : 11/13/2017 01:32:13
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-- \ \ / \
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-- \___\/\___\
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--
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--Command: xaw2vhdl-intstyle /repos/master/dvi_test/ipcore_dir/clock_source.xaw -st clock_source.vhd
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--Design Name: clock_source
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--Device: xc5vfx70t-ff1136-3
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--
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-- Module clock_source
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-- Generated by Xilinx Architecture Wizard
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-- Written for synthesis tool: XST
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-- Period Jitter (unit interval) for block DCM_ADV_INST = 0.024 UI
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-- Period Jitter (Peak-to-Peak) for block DCM_ADV_INST = 0.502 ns
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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entity clock_source is
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port ( CLKIN_IN : in std_logic;
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CLKFX_OUT : out std_logic;
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CLKIN_IBUFG_OUT : out std_logic;
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CLK0_OUT : out std_logic);
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end clock_source;
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architecture BEHAVIORAL of clock_source is
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signal CLKFB_IN : std_logic;
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signal CLKFX_BUF : std_logic;
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signal CLKIN_IBUFG : std_logic;
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signal CLK0_BUF : std_logic;
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signal GND_BIT : std_logic;
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signal GND_BUS_7 : std_logic_vector (6 downto 0);
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signal GND_BUS_16 : std_logic_vector (15 downto 0);
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begin
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GND_BIT <= '0';
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GND_BUS_7(6 downto 0) <= "0000000";
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GND_BUS_16(15 downto 0) <= "0000000000000000";
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CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
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CLK0_OUT <= CLKFB_IN;
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CLKFX_BUFG_INST : BUFG
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port map (I=>CLKFX_BUF,
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O=>CLKFX_OUT);
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CLKIN_IBUFG_INST : IBUFG
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port map (I=>CLKIN_IN,
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O=>CLKIN_IBUFG);
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CLK0_BUFG_INST : BUFG
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port map (I=>CLK0_BUF,
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O=>CLKFB_IN);
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DCM_ADV_INST : DCM_ADV
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generic map( CLK_FEEDBACK => "1X",
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 25,
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CLKFX_MULTIPLY => 12,
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 10.000,
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CLKOUT_PHASE_SHIFT => "NONE",
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DCM_AUTOCALIBRATION => TRUE,
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DCM_PERFORMANCE_MODE => "MAX_SPEED",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => x"F0F0",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE,
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SIM_DEVICE => "VIRTEX5")
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port map (CLKFB=>CLKFB_IN,
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CLKIN=>CLKIN_IBUFG,
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DADDR(6 downto 0)=>GND_BUS_7(6 downto 0),
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DCLK=>GND_BIT,
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DEN=>GND_BIT,
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DI(15 downto 0)=>GND_BUS_16(15 downto 0),
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DWE=>GND_BIT,
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PSCLK=>GND_BIT,
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PSEN=>GND_BIT,
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PSINCDEC=>GND_BIT,
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RST=>GND_BIT,
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CLKDV=>open,
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CLKFX=>CLKFX_BUF,
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CLKFX180=>open,
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CLK0=>CLK0_BUF,
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CLK2X=>open,
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CLK2X180=>open,
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CLK90=>open,
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CLK180=>open,
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CLK270=>open,
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DO=>open,
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DRDY=>open,
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LOCKED=>open,
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PSDONE=>open);
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end BEHAVIORAL;
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