32 lines
999 B
Scala
32 lines
999 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.xilinxvc707pciex1
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import Chisel._
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import diplomacy.LazyModule
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import rocketchip.{
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HasTopLevelNetworks,
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HasTopLevelNetworksModule,
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HasTopLevelNetworksBundle
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}
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import uncore.tilelink2.TLWidthWidget
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trait HasPeripheryXilinxVC707PCIeX1 extends HasTopLevelNetworks {
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val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
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fsb.node := xilinxvc707pcie.master
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xilinxvc707pcie.slave := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
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xilinxvc707pcie.control := TLWidthWidget(socBusConfig.beatBytes)(socBus.node)
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intBus.intnode := xilinxvc707pcie.intnode
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}
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trait HasPeripheryXilinxVC707PCIeX1Bundle extends HasTopLevelNetworksBundle {
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val xilinxvc707pcie = new XilinxVC707PCIeX1IO
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}
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trait HasPeripheryXilinxVC707PCIeX1Module extends HasTopLevelNetworksModule {
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val outer: HasPeripheryXilinxVC707PCIeX1
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val io: HasPeripheryXilinxVC707PCIeX1Bundle
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io.xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port
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}
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