43 lines
1.2 KiB
Scala
43 lines
1.2 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
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class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
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val sck = pingen()
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val dq = Vec(4, pingen())
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val cs = Vec(c.csWidth, pingen())
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override def cloneType: this.type =
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this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
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}
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class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c) {
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override def cloneType: this.type =
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this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
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def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool,
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syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
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withClockAndReset(clock, reset) {
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sck.outputPin(spi.sck, ds = driveStrength)
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(dq zip spi.dq).foreach {case (p, s) =>
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p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
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p.o.oe := s.oe
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p.o.ie := ~s.oe
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s.i := ShiftRegister(p.i.ival, syncStages)
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}
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(cs zip spi.cs) foreach { case (c, s) =>
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c.outputPin(s, ds = driveStrength)
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}
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}
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}
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}
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