9 Commits

Author	SHA1	Message	Date
Henry Cook	fb9dd31374	Refactor package hierarchy. (#25)	2017-07-07 10:48:57 -07:00
Wesley W. Terpstra	66b2fd11bd	vc707 axi enhancements (#24) ... 1 - Print AXI-ID mappings 2 - Use half as many Deinterleaver buffers for the L2 backside 3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)	2017-06-30 12:36:33 -07:00
Wesley W. Terpstra	0ed21ba465	xilinxvc707pciex1: push to a dedicated clock domain	2017-05-12 23:02:44 -07:00
Wesley W. Terpstra	178ac84b59	xilinxvc707pciex1: better wrapper for AXI4-Lite control node (#12)	2017-05-08 01:08:37 -07:00
Wesley W. Terpstra	a24fa9b444	axi4: switch to new pipelined converters	2017-04-26 13:10:50 -07:00
Wesley W. Terpstra	46aa6b0ac4	devices: include DTS meta-data	2017-03-02 20:39:30 -08:00
Wesley W. Terpstra	d61d86e084	xilinx pcie: put buffers before the outputs to the controller	2017-01-20 22:38:27 -08:00
Wesley W. Terpstra	1443834186	xilinx pcie: bytes, not bits ... This bug amazingly compiled correctly and ran correctly! It was saved by the AXIFragmenter which turned the "narrow burst" into individual beats that then got converted to 64b in TileLink land via inspection of the mask bits. The consequence is that AXI bus mastering proceeded at one word per DDR round-trip. Now it is one cache line per DDR round-trip. When we get L2 back in the design, it should really fly!	2016-12-06 16:13:12 -08:00
SiFive	7916ef5249	Initial commit.	2016-11-29 04:08:44 -08:00