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12 Commits

Author SHA1 Message Date
Henry Cook 9ae6413273 periphery: peripherals now in coreplex (#26) 
* periphery: peripherals now in coreplex

* use fromAsyncFIFOMaster
 2017-07-23 08:31:44 -07:00
Henry Cook fb9dd31374 Refactor package hierarchy. (#25) 2017-07-07 10:48:57 -07:00
Wesley W. Terpstra 66b2fd11bd vc707 axi enhancements (#24) 
1 - Print AXI-ID mappings
2 - Use half as many Deinterleaver buffers for the L2 backside
3 - Limit the Q depth on the PCIe control port to 2 (was 1584!)
 2017-06-30 12:36:33 -07:00
Wesley W. Terpstra 886680af49 mig: fix MemoryDevice to use 'reg' properly 2017-06-29 13:41:30 -07:00
Wesley W. Terpstra 3d8c502fce diplomacy: add reg-names to devices (#22) 2017-06-28 17:45:18 -07:00
Wesley W. Terpstra c4c158963c vc707mig: use an external ibuf 
This makes it possible to also drive a PLL of our own from the crystal.
 2017-05-12 23:07:10 -07:00
Wesley W. Terpstra b3f9607512 xilinx mig: put a buffer infront of the controller (#13) 
This makes placement of the L2 and DDR controller easier.
 2017-05-11 11:50:07 -07:00
Wesley W. Terpstra a24fa9b444 axi4: switch to new pipelined converters 2017-04-26 13:10:50 -07:00
Henry Styles b882d6da93 Use _chisel3 analog for MIG inout 2017-04-25 10:15:00 -07:00
Wesley W. Terpstra 46aa6b0ac4 devices: include DTS meta-data 2017-03-02 20:39:30 -08:00
Wesley W. Terpstra c68e44ec55 mig: track change to Blind port API in rocket 2017-01-19 19:53:03 -08:00
SiFive 7916ef5249 Initial commit. 2016-11-29 04:08:44 -08:00