From ef8139f18c1f0392fe7f5b56953e059aca0a98c9 Mon Sep 17 00:00:00 2001
From: Alex Solomatnikov <sols@sifive.com>
Date: Thu, 22 Feb 2018 18:43:39 -0800
Subject: [PATCH] Do not allow status read if status.transferInProgress is
 going to change next cycle

---
 src/main/scala/devices/i2c/I2C.scala | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/devices/i2c/I2C.scala b/src/main/scala/devices/i2c/I2C.scala
index d767a26..be7ff4a 100644
--- a/src/main/scala/devices/i2c/I2C.scala
+++ b/src/main/scala/devices/i2c/I2C.scala
@@ -514,11 +514,14 @@ trait HasI2CModuleContents extends MultiIOModule with HasRegMap {
     status.arbLost          := false.B
   }
   status.transferInProgress := cmd.read || cmd.write
-  status.irqFlag            := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck
+  status.irqFlag            := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck // interrupt request flag is always generated
 
 
   val statusReadReady = Reg(init = true.B)
-  when (!statusReadReady) {
+  when (cmdAck || arbLost) {    // => cmd.read or cmd.write deassert 1 cycle later => transferInProgress deassert 2 cycles later
+    statusReadReady := false.B  // do not allow status read if status.transferInProgress is going to change
+  }
+  .elsewhen (!statusReadReady) {
     statusReadReady := true.B
   }