riscv/sifive-blocks
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Remove pluralization on interface names. Require clocks and resets explicitly when necessary

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This commit is contained in:
Megan Wachs
2017-07-19 14:51:50 -07:00
parent 4d74e8f67f
commit ef4f2ed888
10 changed files with 74 additions and 49 deletions
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10
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -21,15 +21,15 @@ trait HasPeripherySPI extends HasSystemNetworks {
}
trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO]
val spi: HeterogeneousBag[SPIPortIO]
}
trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
val outer: HasPeripherySPI
val spis = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
(spis zip outer.spis).foreach { case (io, device) =>
(spi zip outer.spis).foreach { case (io, device) =>
io <> device.module.io.port
}
}
@ -38,7 +38,7 @@ case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
trait HasPeripherySPIFlash extends HasSystemNetworks {
val spiFlashParams = p(PeripherySPIFlashKey)
val qspi = spiFlashParams map { params =>
val qspis = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
@ -56,7 +56,7 @@ trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeriphe
val outer: HasPeripherySPIFlash
val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
(qspi zip outer.qspi) foreach { case (io, device) =>
(qspi zip outer.qspis) foreach { case (io, device) =>
io <> device.module.io.port
}
}

26
src/main/scala/devices/spi/SPIPins.scala
View File

@ -2,6 +2,7 @@
package sifive.blocks.devices.spi
import Chisel._
import chisel3.experimental.{withClockAndReset}
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
@ -10,19 +11,22 @@ class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c)
val dq: Vec[T] = Vec(4, pingen())
val cs: Vec[T] = Vec(c.csWidth, pingen())
def fromSPIPort(spi: SPIPortIO, syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
sck.outputPin(spi.sck, ds = driveStrength)
def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
(dq zip spi.dq).foreach {case (p, s) =>
p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
p.o.oe := s.oe
p.o.ie := ~s.oe
s.i := ShiftRegister(p.i.ival, syncStages)
}
withClockAndReset(clock, reset) {
sck.outputPin(spi.sck, ds = driveStrength)
(cs zip spi.cs) foreach { case (c, s) =>
c.outputPin(s, ds = driveStrength)
(dq zip spi.dq).foreach {case (p, s) =>
p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
p.o.oe := s.oe
p.o.ie := ~s.oe
s.i := ShiftRegister(p.i.ival, syncStages)
}
(cs zip spi.cs) foreach { case (c, s) =>
c.outputPin(s, ds = driveStrength)
}
}
}
}