64 lines
2.0 KiB
Scala
64 lines
2.0 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.spi
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import Chisel._
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
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import freechips.rocketchip.chip.HasSystemNetworks
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import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
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import freechips.rocketchip.util.HeterogeneousBag
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case object PeripherySPIKey extends Field[Seq[SPIParams]]
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trait HasPeripherySPI extends HasSystemNetworks {
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val spiParams = p(PeripherySPIKey)
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val spis = spiParams map { params =>
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val spi = LazyModule(new TLSPI(peripheryBusBytes, params))
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spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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intBus.intnode := spi.intnode
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spi
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}
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}
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trait HasPeripherySPIBundle {
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val spi: HeterogeneousBag[SPIPortIO]
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}
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trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIBundle {
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val outer: HasPeripherySPI
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val spi = IO(HeterogeneousBag(outer.spiParams.map(new SPIPortIO(_))))
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(spi zip outer.spis).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
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trait HasPeripherySPIFlash extends HasSystemNetworks {
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val spiFlashParams = p(PeripherySPIFlashKey)
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val qspis = spiFlashParams map { params =>
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val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
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qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
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qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
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intBus.intnode := qspi.intnode
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qspi
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}
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}
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trait HasPeripherySPIFlashBundle {
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val qspi: HeterogeneousBag[SPIPortIO]
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}
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trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeripherySPIFlashBundle {
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val outer: HasPeripherySPIFlash
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val qspi = IO(HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))))
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(qspi zip outer.qspis) foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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