riscv/sifive-blocks
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GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.

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This commit is contained in:
Megan Wachs 2017-06-12 17:53:51 -07:00
parent 7c118790cb
commit b06b80dccd
3 changed files with 6 additions and 6 deletions
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4
src/main/scala/devices/i2c/I2CPeriphery.scala
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@ -22,8 +22,8 @@ trait HasPeripheryI2C extends HasSystemNetworks {
trait HasPeripheryI2CBundle { trait HasPeripheryI2CBundle {
val i2cs: Vec[I2CPort] val i2cs: Vec[I2CPort]
def toGPIOPins(dummy: Int = 1): Seq[I2CGPIOPort] = i2cs.map { i => def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i =>
val pin = Module(new I2CGPIOPort) val pin = Module(new I2CGPIOPort(syncStages))
pin.io.i2c <> i pin.io.i2c <> i
pin pin
} }

4
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -23,8 +23,8 @@ trait HasPeripherySPI extends HasSystemNetworks {
trait HasPeripherySPIBundle { trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO] val spis: HeterogeneousBag[SPIPortIO]
def SPItoGPIOPins(sync_stages: Int = 0): Seq[SPIGPIOPort] = spis.map { s => def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
val pin = Module(new SPIGPIOPort(s.c, sync_stages)) val pin = Module(new SPIGPIOPort(s.c, syncStages))
pin.io.spi <> s pin.io.spi <> s
pin pin
} }

4
src/main/scala/devices/uart/UARTPeriphery.scala
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@ -29,8 +29,8 @@ trait HasPeripheryUARTBundle {
uarts.foreach { _.rxd := UInt(1) } uarts.foreach { _.rxd := UInt(1) }
} }
def UARTtoGPIOPins(sync_stages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u => def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u =>
val pin = Module(new UARTGPIOPort(sync_stages)) val pin = Module(new UARTGPIOPort(syncStages))
pin.io.uart <> u pin.io.uart <> u
pin pin
} }