From b06b80dccdf4e71b37866cc0e32a800a2b1a62d1 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Mon, 12 Jun 2017 17:53:51 -0700 Subject: [PATCH] GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful. --- src/main/scala/devices/i2c/I2CPeriphery.scala | 4 ++-- src/main/scala/devices/spi/SPIPeriphery.scala | 4 ++-- src/main/scala/devices/uart/UARTPeriphery.scala | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/devices/i2c/I2CPeriphery.scala b/src/main/scala/devices/i2c/I2CPeriphery.scala index a79f94c..d9c3ff4 100644 --- a/src/main/scala/devices/i2c/I2CPeriphery.scala +++ b/src/main/scala/devices/i2c/I2CPeriphery.scala @@ -22,8 +22,8 @@ trait HasPeripheryI2C extends HasSystemNetworks { trait HasPeripheryI2CBundle { val i2cs: Vec[I2CPort] - def toGPIOPins(dummy: Int = 1): Seq[I2CGPIOPort] = i2cs.map { i => - val pin = Module(new I2CGPIOPort) + def toGPIOPins(syncStages: Int = 0): Seq[I2CGPIOPort] = i2cs.map { i => + val pin = Module(new I2CGPIOPort(syncStages)) pin.io.i2c <> i pin } diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index bd77259..4361b1a 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -23,8 +23,8 @@ trait HasPeripherySPI extends HasSystemNetworks { trait HasPeripherySPIBundle { val spis: HeterogeneousBag[SPIPortIO] - def SPItoGPIOPins(sync_stages: Int = 0): Seq[SPIGPIOPort] = spis.map { s => - val pin = Module(new SPIGPIOPort(s.c, sync_stages)) + def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIGPIOPort] = spis.map { s => + val pin = Module(new SPIGPIOPort(s.c, syncStages)) pin.io.spi <> s pin } diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala index 05c4a33..1f8011e 100644 --- a/src/main/scala/devices/uart/UARTPeriphery.scala +++ b/src/main/scala/devices/uart/UARTPeriphery.scala @@ -29,8 +29,8 @@ trait HasPeripheryUARTBundle { uarts.foreach { _.rxd := UInt(1) } } - def UARTtoGPIOPins(sync_stages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u => - val pin = Module(new UARTGPIOPort(sync_stages)) + def UARTtoGPIOPins(syncStages: Int = 0): Seq[UARTGPIOPort] = uarts.map { u => + val pin = Module(new UARTGPIOPort(syncStages)) pin.io.uart <> u pin }