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GPIO/SPI/I2C: Add sync stages in place of dummy variable since we need them and they are more useful.

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This commit is contained in:
Megan Wachs
2017-06-12 17:53:51 -07:00
parent 7c118790cb
commit b06b80dccd
3 changed files with 6 additions and 6 deletions
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4
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -23,8 +23,8 @@ trait HasPeripherySPI extends HasSystemNetworks {
trait HasPeripherySPIBundle {
val spis: HeterogeneousBag[SPIPortIO]
def SPItoGPIOPins(sync_stages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
val pin = Module(new SPIGPIOPort(s.c, sync_stages))
def SPItoGPIOPins(syncStages: Int = 0): Seq[SPIGPIOPort] = spis.map { s =>
val pin = Module(new SPIGPIOPort(s.c, syncStages))
pin.io.spi <> s
pin
}