Initial commit.
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SiFive
158
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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158
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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// See LICENSE for license details.
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package sifive.blocks.devices.xilinxvc707mig
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import Chisel._
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import config._
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import diplomacy._
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import uncore.tilelink2._
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import uncore.axi4._
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import rocketchip._
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import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGUnidirectionalIOClocksReset, VC707MIGUnidirectionalIODDR, vc707mig}
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trait HasXilinxVC707MIGParameters {
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}
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class XilinxVC707MIGPads extends Bundle with VC707MIGUnidirectionalIODDR {
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val _inout_ddr3_dq = Bits(OUTPUT,64)
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val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
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val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
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}
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class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
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with VC707MIGUnidirectionalIOClocksReset {
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val _inout_ddr3_dq = Bits(OUTPUT,64)
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val _inout_ddr3_dqs_n = Bits(OUTPUT,8)
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val _inout_ddr3_dqs_p = Bits(OUTPUT,8)
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}
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class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
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val node = TLInputNode()
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val axi4 = AXI4InternalOutputNode(AXI4SlavePortParameters(
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slaves = Seq(AXI4SlaveParameters(
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address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
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regionType = RegionType.UNCACHED,
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executable = true,
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supportsWrite = TransferSizes(1, 256*8),
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supportsRead = TransferSizes(1, 256*8),
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interleavedId = Some(0))),
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beatBytes = 8))
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val xing = LazyModule(new TLAsyncCrossing)
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val toaxi4 = LazyModule(new TLToAXI4(idBits = 4))
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xing.node := node
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val monitor = (toaxi4.node := xing.node)
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axi4 := toaxi4.node
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val port = new XilinxVC707MIGIO
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val tl = node.bundleIn
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}
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//MIG black box instantiation
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val blackbox = Module(new vc707mig)
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//pins to top level
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//inouts
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io.port._inout_ddr3_dq := blackbox.io.ddr3_dq
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io.port._inout_ddr3_dqs_n := blackbox.io.ddr3_dqs_n
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io.port._inout_ddr3_dqs_p := blackbox.io.ddr3_dqs_p
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//outputs
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io.port.ddr3_addr := blackbox.io.ddr3_addr
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io.port.ddr3_ba := blackbox.io.ddr3_ba
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io.port.ddr3_ras_n := blackbox.io.ddr3_ras_n
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io.port.ddr3_cas_n := blackbox.io.ddr3_cas_n
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io.port.ddr3_we_n := blackbox.io.ddr3_we_n
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io.port.ddr3_reset_n := blackbox.io.ddr3_reset_n
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io.port.ddr3_ck_p := blackbox.io.ddr3_ck_p
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io.port.ddr3_ck_n := blackbox.io.ddr3_ck_n
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io.port.ddr3_cke := blackbox.io.ddr3_cke
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io.port.ddr3_cs_n := blackbox.io.ddr3_cs_n
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io.port.ddr3_dm := blackbox.io.ddr3_dm
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io.port.ddr3_odt := blackbox.io.ddr3_odt
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//inputs
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//differential system clock
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blackbox.io.sys_clk_n := io.port.sys_clk_n
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blackbox.io.sys_clk_p := io.port.sys_clk_p
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//user interface signals
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val axi_async = axi4.bundleIn(0)
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xing.module.io.in_clock := clock
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xing.module.io.in_reset := reset
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xing.module.io.out_clock := blackbox.io.ui_clk
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xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
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toaxi4.module.clock := blackbox.io.ui_clk
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toaxi4.module.reset := blackbox.io.ui_clk_sync_rst
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monitor.foreach { lm =>
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lm.module.clock := blackbox.io.ui_clk
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lm.module.reset := blackbox.io.ui_clk_sync_rst
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}
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io.port.ui_clk := blackbox.io.ui_clk
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io.port.ui_clk_sync_rst := blackbox.io.ui_clk_sync_rst
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io.port.mmcm_locked := blackbox.io.mmcm_locked
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blackbox.io.aresetn := io.port.aresetn
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blackbox.io.app_sr_req := Bool(false)
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blackbox.io.app_ref_req := Bool(false)
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blackbox.io.app_zq_req := Bool(false)
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//app_sr_active := unconnected
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//app_ref_ack := unconnected
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//app_zq_ack := unconnected
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//slave AXI interface write address ports
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blackbox.io.s_axi_awid := axi_async.aw.bits.id
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blackbox.io.s_axi_awaddr := axi_async.aw.bits.addr //truncation ??
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blackbox.io.s_axi_awlen := axi_async.aw.bits.len
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blackbox.io.s_axi_awsize := axi_async.aw.bits.size
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blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
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blackbox.io.s_axi_awlock := axi_async.aw.bits.lock
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blackbox.io.s_axi_awcache := UInt("b0011")
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blackbox.io.s_axi_awprot := axi_async.aw.bits.prot
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blackbox.io.s_axi_awqos := axi_async.aw.bits.qos
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blackbox.io.s_axi_awvalid := axi_async.aw.valid
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axi_async.aw.ready := blackbox.io.s_axi_awready
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//slave interface write data ports
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blackbox.io.s_axi_wdata := axi_async.w.bits.data
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blackbox.io.s_axi_wstrb := axi_async.w.bits.strb
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blackbox.io.s_axi_wlast := axi_async.w.bits.last
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blackbox.io.s_axi_wvalid := axi_async.w.valid
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axi_async.w.ready := blackbox.io.s_axi_wready
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//slave interface write response
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blackbox.io.s_axi_bready := axi_async.b.ready
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axi_async.b.bits.id := blackbox.io.s_axi_bid
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axi_async.b.bits.resp := blackbox.io.s_axi_bresp
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axi_async.b.valid := blackbox.io.s_axi_bvalid
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//slave AXI interface read address ports
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blackbox.io.s_axi_arid := axi_async.ar.bits.id
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blackbox.io.s_axi_araddr := axi_async.ar.bits.addr //truncation ??
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blackbox.io.s_axi_arlen := axi_async.ar.bits.len
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blackbox.io.s_axi_arsize := axi_async.ar.bits.size
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blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
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blackbox.io.s_axi_arlock := axi_async.ar.bits.lock
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blackbox.io.s_axi_arcache := UInt("b0011")
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blackbox.io.s_axi_arprot := axi_async.ar.bits.prot
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blackbox.io.s_axi_arqos := axi_async.ar.bits.qos
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blackbox.io.s_axi_arvalid := axi_async.ar.valid
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axi_async.ar.ready := blackbox.io.s_axi_arready
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//slace AXI interface read data ports
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blackbox.io.s_axi_rready := axi_async.r.ready
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axi_async.r.bits.id := blackbox.io.s_axi_rid
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axi_async.r.bits.data := blackbox.io.s_axi_rdata
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axi_async.r.bits.resp := blackbox.io.s_axi_rresp
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axi_async.r.bits.last := blackbox.io.s_axi_rlast
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axi_async.r.valid := blackbox.io.s_axi_rvalid
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//misc
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io.port.init_calib_complete := blackbox.io.init_calib_complete
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blackbox.io.sys_rst :=io.port.sys_rst
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//mig.device_temp :- unconnceted
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}
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}
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@ -0,0 +1,26 @@
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// See LICENSE for license details.
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package sifive.blocks.devices.xilinxvc707mig
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import Chisel._
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import diplomacy._
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import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
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import coreplex.BankedL2Config
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trait PeripheryXilinxVC707MIG extends TopNetwork {
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val module: PeripheryXilinxVC707MIGModule
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val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
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require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
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val mem = Seq(xilinxvc707mig.node)
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}
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trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
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val xilinxvc707mig = new XilinxVC707MIGIO
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}
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trait PeripheryXilinxVC707MIGModule extends TopNetworkModule {
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val outer: PeripheryXilinxVC707MIG
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val io: PeripheryXilinxVC707MIGBundle
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io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
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}
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