27 lines
809 B
Scala
27 lines
809 B
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.xilinxvc707mig
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import Chisel._
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import diplomacy._
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import rocketchip.{TopNetwork,TopNetworkModule,TopNetworkBundle}
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import coreplex.BankedL2Config
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trait PeripheryXilinxVC707MIG extends TopNetwork {
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val module: PeripheryXilinxVC707MIGModule
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val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
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require(p(BankedL2Config).nMemoryChannels == 1, "Coreplex must have 1 master memory port")
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val mem = Seq(xilinxvc707mig.node)
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}
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trait PeripheryXilinxVC707MIGBundle extends TopNetworkBundle {
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val xilinxvc707mig = new XilinxVC707MIGIO
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}
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trait PeripheryXilinxVC707MIGModule extends TopNetworkModule {
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val outer: PeripheryXilinxVC707MIG
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val io: PeripheryXilinxVC707MIGBundle
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io.xilinxvc707mig <> outer.xilinxvc707mig.module.io.port
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}
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