riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

"Fix" false combinational loop through SPIArbiter

Browse Source 
Mux1H converts aggregates to UInt, muxes, then converts back which can
look like a cominational loop.
This commit is contained in:
Jack Koenig 2017-03-30 19:12:15 -07:00
parent e2073feef8
commit 6a3b5e1a31
1 changed files with 3 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/devices/spi/SPIArbiter.scala
View File

@ -20,7 +20,9 @@ class SPIArbiter(c: SPIParamsBase, n: Int) extends Module {
io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits)) io.outer.tx.bits := Mux1H(sel, io.inner.map(_.tx.bits))
io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt)) io.outer.cnt := Mux1H(sel, io.inner.map(_.cnt))
io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt)) io.outer.fmt := Mux1H(sel, io.inner.map(_.fmt))
io.outer.cs := Mux1H(sel, io.inner.map(_.cs)) // Workaround for overzealous combinational loop detection
io.outer.cs := Mux(sel(1), io.inner(0).cs, io.inner(1).cs)
require(n == 2, "SPIArbiter currently only supports 2 clients")
(io.inner zip sel).foreach { case (inner, s) => (io.inner zip sel).foreach { case (inner, s) =>
inner.tx.ready := io.outer.tx.ready && s inner.tx.ready := io.outer.tx.ready && s