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SPI: Make it easier to build arbitrary bundles

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This commit is contained in:
Megan Wachs 2017-09-20 16:21:21 -07:00
parent f8dcfbacfa
commit 6a13639cf3
1 changed files with 8 additions and 1 deletions
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9
src/main/scala/devices/spi/SPIPins.scala
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@ -5,7 +5,7 @@ import Chisel._
import chisel3.experimental.{withClockAndReset} import chisel3.experimental.{withClockAndReset}
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin} import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) { class SPISignals[T <: Data] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
val sck = pingen() val sck = pingen()
val dq = Vec(4, pingen()) val dq = Vec(4, pingen())
@ -14,6 +14,13 @@ class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c)
override def cloneType: this.type = override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type] this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
}
class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPISignals(pingen, c) {
override def cloneType: this.type =
this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool, def fromPort(spi: SPIPortIO, clock: Clock, reset: Bool,
syncStages: Int = 0, driveStrength: Bool = Bool(false)) { syncStages: Int = 0, driveStrength: Bool = Bool(false)) {