riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

Renamed i2cDevices to i2c

Browse Source
This commit is contained in:
Alex Solomatnikov 2017-02-06 10:39:47 -08:00
parent d474b5ceb2
commit 5a0d084b38
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/devices/i2c/I2CPeriphery.scala
View File

@ -8,7 +8,7 @@ import uncore.tilelink2.TLFragmenter
trait PeripheryI2C { trait PeripheryI2C {
this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } => this: TopNetwork { val i2cConfigs: Seq[I2CConfig] } =>
val i2cDevices = i2cConfigs.zipWithIndex.map { case (c, i) => val i2c = i2cConfigs.zipWithIndex.map { case (c, i) =>
val i2c = LazyModule(new TLI2C(c)) val i2c = LazyModule(new TLI2C(c))
i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node) i2c.node := TLFragmenter(peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := i2c.intnode intBus.intnode := i2c.intnode
@ -27,7 +27,7 @@ trait PeripheryI2CModule {
val outer: PeripheryI2C val outer: PeripheryI2C
val io: PeripheryI2CBundle val io: PeripheryI2CBundle
} => } =>
(io.i2cs zip outer.i2cDevices).foreach { case (io, device) => (io.i2cs zip outer.i2c).foreach { case (io, device) =>
io <> device.module.io.port io <> device.module.io.port
} }
} }