From fb4977b518d20fcb3a5011a2725425b1ad709efa Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Wed, 7 Mar 2018 09:54:56 -0800 Subject: [PATCH] SPI: Use the standard synchronizer primitive for the SPI DQ inputs --- src/main/scala/devices/spi/SPIPins.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/devices/spi/SPIPins.scala b/src/main/scala/devices/spi/SPIPins.scala index f8ce8e1..ea5cfc5 100644 --- a/src/main/scala/devices/spi/SPIPins.scala +++ b/src/main/scala/devices/spi/SPIPins.scala @@ -3,6 +3,7 @@ package sifive.blocks.devices.spi import Chisel._ import chisel3.experimental.{withClockAndReset} +import freechips.rocketchip.util.{SynchronizerShiftReg} import sifive.blocks.devices.pinctrl.{PinCtrl, Pin} class SPISignals[T <: Data](private val pingen: () => T, c: SPIParamsBase) extends SPIBundle(c) { @@ -22,11 +23,11 @@ object SPIPinsFromPort { withClockAndReset(clock, reset) { pins.sck.outputPin(spi.sck, ds = driveStrength) - (pins.dq zip spi.dq).foreach {case (p, s) => + (pins.dq zip spi.dq).zipWithIndex.foreach {case ((p, s), i) => p.outputPin(s.o, pue = Bool(true), ds = driveStrength) p.o.oe := s.oe p.o.ie := ~s.oe - s.i := ShiftRegister(p.i.ival, syncStages) + s.i := SynchronizerShiftReg(p.i.ival, syncStages, name = Some(s"spi_dq_${i}_sync")) } (pins.cs zip spi.cs) foreach { case (c, s) =>