devices: include DTS meta-data
This commit is contained in:
committed by
Henry Cook
parent
baccd5ada2
commit
46aa6b0ac4
@ -23,12 +23,13 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
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val slave = TLInputNode()
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val control = TLInputNode()
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val master = TLOutputNode()
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val intnode = IntSourceNode(1)
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val intnode = IntOutputNode()
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val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
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axi_to_pcie_x1.slave := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
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axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
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master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
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intnode := axi_to_pcie_x1.intnode
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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@ -40,7 +41,6 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
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}
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io.port <> axi_to_pcie_x1.module.io.port
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io.interrupt(0)(0) := axi_to_pcie_x1.module.io.interrupt_out
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//PCIe Reference Clock
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val ibufds_gte2 = Module(new IBUFDS_GTE2)
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