devices: include DTS meta-data

src/main/scala/devices/gpio/GPIO.scala

@@ -286,6 +286,6 @@ object GPIOInputPinCtrl {
 
 // Magic TL2 Incantation to create a TL2 Slave
 class TLGPIO(w: Int, c: GPIOParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = c.width, beatBytes = w)(
+  extends TLRegisterRouter(c.address, "gpio", Seq("sifive,gpio0"), interrupts = c.width, beatBytes = w)(
   new TLRegBundle(c, _)    with HasGPIOBundleContents)(
   new TLRegModule(c, _, _) with HasGPIOModuleContents)

src/main/scala/devices/i2c/I2C.scala

@@ -535,6 +535,6 @@ trait HasI2CModuleContents extends Module with HasRegMap {
 
 // Magic TL2 Incantation to create a TL2 Slave
 class TLI2C(w: Int, c: I2CParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
+  extends TLRegisterRouter(c.address, "i2c", Seq("sifive,i2c0"), interrupts = 1, beatBytes = w)(
   new TLRegBundle(c, _)    with HasI2CBundleContents)(
   new TLRegModule(c, _, _) with HasI2CModuleContents)

src/main/scala/devices/mockaon/MockAON.scala

@@ -95,6 +95,6 @@ trait HasMockAONModuleContents extends Module with HasRegMap {
 }
 
 class TLMockAON(w: Int, c: MockAONParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
+  extends TLRegisterRouter(c.address, "aon", Seq("sifive,aon0"), interrupts = 2, size = c.size, beatBytes = w, concurrency = 1)(
   new TLRegBundle(c, _)    with HasMockAONBundleContents)(
   new TLRegModule(c, _, _) with HasMockAONModuleContents)

src/main/scala/devices/pwm/PWM.scala

@@ -62,6 +62,6 @@ trait HasPWMModuleContents extends Module with HasRegMap {
 }
 
 class TLPWM(w: Int, c: PWMParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = c.ncmp, size = c.size, beatBytes = w)(
+  extends TLRegisterRouter(c.address, "pwm", Seq("sifive,pwm0"), interrupts = c.ncmp, size = c.size, beatBytes = w)(
   new TLRegBundle(c, _)    with HasPWMBundleContents)(
   new TLRegModule(c, _, _) with HasPWMModuleContents)

src/main/scala/devices/spi/TLSPI.scala

@@ -109,8 +109,9 @@ class SPITopModule[B <: SPITopBundle](c: SPIParamsBase, bundle: => B, outer: TLS
 
 abstract class TLSPIBase(w: Int, c: SPIParamsBase)(implicit p: Parameters) extends LazyModule {
   require(isPow2(c.rSize))
-  val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), beatBytes = w)
-  val intnode = IntSourceNode(1)
+  val device = new SimpleDevice("spi", Seq("sifive,spi0"))
+  val rnode = TLRegisterNode(address = AddressSet(c.rAddress, c.rSize-1), device = device, beatBytes = w)
+  val intnode = IntSourceNode(IntSourcePortSimple(resources = device.int))
 }
 
 class TLSPI(w: Int, c: SPIParams)(implicit p: Parameters) extends TLSPIBase(w,c)(p) {

src/main/scala/devices/uart/UART.scala

@@ -260,6 +260,6 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
 
 // Magic TL2 Incantation to create a TL2 UART
 class TLUART(w: Int, c: UARTParams)(implicit p: Parameters)
-  extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = w)(
+  extends TLRegisterRouter(c.address, "serial", Seq("sifive,uart0"), interrupts = 1, beatBytes = w)(
   new TLRegBundle(c, _)    with HasUARTTopBundleContents)(
   new TLRegModule(c, _, _) with HasUARTTopModuleContents)

src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala

@@ -26,10 +26,12 @@ class XilinxVC707MIGIO extends Bundle with VC707MIGUnidirectionalIODDR
 }
 
 class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
+  val device = new MemoryDevice
   val node = TLInputNode()
   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
     slaves = Seq(AXI4SlaveParameters(
       address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
+      resources     = device.reg,
       regionType    = RegionType.UNCACHED,
       executable    = true,
       supportsWrite = TransferSizes(1, 256*8),

src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1.scala

@@ -23,12 +23,13 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
   val slave = TLInputNode()
   val control = TLInputNode()
   val master = TLOutputNode()
-  val intnode = IntSourceNode(1)
+  val intnode = IntOutputNode()
 
   val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
   axi_to_pcie_x1.slave   := AXI4Buffer()(TLToAXI4(idBits=4)(slave))
   axi_to_pcie_x1.control := AXI4Buffer()(AXI4Fragmenter(lite=true, maxInFlight=4)(TLToAXI4(idBits=0)(control)))
   master := TLWidthWidget(8)(AXI4ToTL()(AXI4Fragmenter()(axi_to_pcie_x1.master)))
+  intnode := axi_to_pcie_x1.intnode
 
   lazy val module = new LazyModuleImp(this) {
     val io = new Bundle {
@@ -40,7 +41,6 @@ class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
     }
 
     io.port <> axi_to_pcie_x1.module.io.port
-    io.interrupt(0)(0) := axi_to_pcie_x1.module.io.interrupt_out
 
     //PCIe Reference Clock
     val ibufds_gte2 = Module(new IBUFDS_GTE2)