riscv/sifive-blocks
1
0
Fork 0
Code Releases Activity

Bug fix: arbLost should be asserted when bitState =/= s_bit_idle (#49)

Browse Source
This commit is contained in:
solomatnikov 2018-02-23 12:09:18 -08:00 committed by GitHub
parent 462976a070
commit 3dee152775
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/devices/i2c/I2C.scala
View File

@ -202,7 +202,7 @@ trait HasI2CModuleContents extends MultiIOModule with HasRegMap {
s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18) s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18)
val bitState = Reg(init = s_bit_idle) val bitState = Reg(init = s_bit_idle)
val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState === s_bit_idle) && stopCond && !bitCmdStop)) val arbLost = Reg(init = false.B, next = (sdaChk && !sSDA && sdaOen) | ((bitState =/= s_bit_idle) && stopCond && !bitCmdStop))
// bit FSM // bit FSM
when (arbLost) { when (arbLost) {