Completed Chisel RTL (not tested yet)
This commit is contained in:
Alex Solomatnikov
parent
9d2a173b15
commit
2cc1012fa2
@ -3,6 +3,7 @@ package sifive.blocks.devices.i2c
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import Chisel._
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import config._
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import util._
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import regmapper._
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import uncore.tilelink2._
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import rocketchip.PeripheryBusConfig
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@ -35,22 +36,477 @@ trait I2CBundle extends Bundle with HasI2CParameters {
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trait I2CModule extends Module with HasI2CParameters with HasRegMap {
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val io: I2CBundle
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val prescaler_lo = Reg(UInt(8.W)) // low byte clock prescaler register
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val prescaler_hi = Reg(UInt(8.W)) // high byte clock prescaler register
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val control = Reg(UInt(8.W)) // control register
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val data = Reg(UInt(8.W)) // write: transmit byte, read: receive byte
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val cmd_status = Reg(UInt(8.W)) // write: command, read: status
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val I2C_CMD_NOP = UInt(0x00)
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val I2C_CMD_START = UInt(0x01)
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val I2C_CMD_STOP = UInt(0x02)
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val I2C_CMD_WRITE = UInt(0x04)
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val I2C_CMD_READ = UInt(0x08)
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class PrescalerBundle extends Bundle{
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val hi = UInt(8.W)
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val lo = UInt(8.W)
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}
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class ControlBundle extends Bundle{
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val coreEn = Bool()
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val intEn = Bool()
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val reserved = UInt(6.W)
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}
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class CommandBundle extends Bundle{
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val start = Bool()
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val stop = Bool()
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val read = Bool()
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val write = Bool()
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val ack = Bool()
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val reserved = UInt(2.W)
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val irqAck = Bool()
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}
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class StatusBundle extends Bundle{
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val receivedAck = Bool() // received aknowledge from slave
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val busy = Bool()
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val arbLost = Bool()
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val reserved = UInt(3.W)
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val transferInProgress = Bool()
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val irqFlag = Bool()
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}
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// control state visible to SW/driver
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val prescaler = Reg(init = (new PrescalerBundle).fromBits(0xFFFF.U))
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val control = Reg(init = (new ControlBundle).fromBits(0.U))
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val transmitData = Reg(init = UInt(0, 8.W))
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val receivedData = Reg(init = UInt(0, 8.W))
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val cmd = Reg(init = (new CommandBundle).fromBits(0.U))
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val status = Reg(init = (new StatusBundle).fromBits(0.U))
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//////// Bit level ////////
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io.port.scl.out := false.B // i2c clock line output
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io.port.sda.out := false.B // i2c data line output
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// filter SCL and SDA signals; (attempt to) remove glitches
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val filterCnt = Reg(init = UInt(0, 14.W))
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when ( !control.coreEn ) {
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filterCnt := 0.U
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} .elsewhen (~(filterCnt.orR)) {
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filterCnt := Cat(prescaler.hi, prescaler.lo) >> 2 //16x I2C bus frequency
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} .otherwise {
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filterCnt := filterCnt - 1.U
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}
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val fSCL = Reg(init = UInt(0x7, 3.W))
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val fSDA = Reg(init = UInt(0x7, 3.W))
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when (~(filterCnt.orR)) {
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fSCL := Cat(fSCL, io.port.scl.in)
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fSDA := Cat(fSDA, io.port.sda.in)
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}
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val sSCL = Reg(init = Bool(true), next = (new Majority(fSCL.toBools.toSet)).out)
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val sSDA = Reg(init = Bool(true), next = (new Majority(fSDA.toBools.toSet)).out)
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val dSCL = Reg(init = Bool(true), next = sSCL)
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val dSDA = Reg(init = Bool(true), next = sSDA)
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val dSCLOen = Reg(next = io.port.scl.oe) // delayed scl_oen
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// detect start condition => detect falling edge on SDA while SCL is high
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// detect stop condition => detect rising edge on SDA while SCL is high
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val startCond = Reg(init = Bool(false), next = !sSDA && dSDA && sSCL)
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val stopCond = Reg(init = Bool(false), next = sSDA && !dSDA && sSCL)
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// master drives SCL high, but another master pulls it low
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// master start counting down its low cycle now (clock synchronization)
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val sclSync = dSCL && !sSCL && io.port.scl.oe
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// slave_wait is asserted when master wants to drive SCL high, but the slave pulls it low
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// slave_wait remains asserted until the slave releases SCL
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val slaveWait = Reg(init = Bool(false))
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slaveWait := (io.port.scl.oe && !dSCLOen && !sSCL) || (slaveWait && !sSCL)
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val clkEn = Reg(init = Bool(true)) // clock generation signals
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val cnt = Reg(init = UInt(0, 16.W)) // clock divider counter (synthesis)
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// generate clk enable signal
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when (~(cnt.orR) || !control.coreEn || sclSync ) {
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cnt := Cat(prescaler.hi, prescaler.lo)
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clkEn := true.B
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}
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.elsewhen (slaveWait) {
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clkEn := false.B
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}
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.otherwise {
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cnt := cnt - 1.U
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clkEn := false.B
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}
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val sclOen = Reg(init = Bool(true))
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io.port.scl.oe := sclOen
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val sdaOen = Reg(init = Bool(true))
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io.port.sda.oe := sdaOen
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val sdaChk = Reg(init = Bool(false)) // check SDA output (Multi-master arbitration)
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val transmitBit = Reg(init = Bool(false))
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val receivedBit = Reg(Bool())
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when (sSCL && !dSCL) {
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receivedBit := sSDA
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}
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val bitCmd = Reg(init = UInt(0, 4.W)) // command (from byte controller)
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val bitCmdStop = Reg(init = Bool(false))
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when (clkEn) {
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bitCmdStop := bitCmd === I2C_CMD_STOP
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}
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val bitCmdAck = Reg(init = Bool(false))
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val (s_bit_idle ::
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s_bit_start_a :: s_bit_start_b :: s_bit_start_c :: s_bit_start_d :: s_bit_start_e ::
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s_bit_stop_a :: s_bit_stop_b :: s_bit_stop_c :: s_bit_stop_d ::
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s_bit_rd_a :: s_bit_rd_b :: s_bit_rd_c :: s_bit_rd_d ::
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s_bit_wr_a :: s_bit_wr_b :: s_bit_wr_c :: s_bit_wr_d :: Nil) = Enum(UInt(), 18)
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val bitState = Reg(init = s_bit_idle)
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val arbLost = Reg(init = Bool(false), next = (sdaChk && !sSDA && sdaOen) | ((bitState === s_bit_idle) && stopCond && !bitCmdStop))
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// bit FSM
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when (arbLost) {
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bitState := s_bit_idle
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bitCmdAck := false.B
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sclOen := true.B
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sdaOen := true.B
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sdaChk := false.B
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}
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.otherwise {
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bitCmdAck := false.B
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when (clkEn) {
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switch (bitState) {
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is (s_bit_idle) {
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switch (bitCmd) {
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is (I2C_CMD_START) { bitState := s_bit_start_a }
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is (I2C_CMD_STOP) { bitState := s_bit_stop_a }
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is (I2C_CMD_WRITE) { bitState := s_bit_wr_a }
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is (I2C_CMD_READ) { bitState := s_bit_rd_a }
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}
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sdaChk := false.B
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}
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is (s_bit_start_a) {
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bitState := s_bit_start_b
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sclOen := sclOen
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sdaOen := true.B
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sdaChk := false.B
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}
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is (s_bit_start_b) {
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bitState := s_bit_start_c
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sclOen := true.B
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sdaOen := true.B
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sdaChk := false.B
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}
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is (s_bit_start_c) {
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bitState := s_bit_start_d
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sclOen := true.B
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sdaOen := false.B
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sdaChk := false.B
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}
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is (s_bit_start_d) {
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bitState := s_bit_start_e
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sclOen := true.B
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sdaOen := false.B
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sdaChk := false.B
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}
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is (s_bit_start_e) {
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bitState := s_bit_idle
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bitCmdAck := true.B
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sclOen := false.B
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sdaOen := false.B
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sdaChk := false.B
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}
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is (s_bit_stop_a) {
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bitState := s_bit_stop_b
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sclOen := false.B
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sdaOen := false.B
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sdaChk := false.B
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}
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is (s_bit_stop_b) {
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bitState := s_bit_stop_c
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sclOen := true.B
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sdaOen := false.B
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sdaChk := false.B
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}
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is (s_bit_stop_c) {
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bitState := s_bit_stop_d
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sclOen := true.B
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sdaOen := false.B
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sdaChk := false.B
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}
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is (s_bit_stop_d) {
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bitState := s_bit_idle
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bitCmdAck := true.B
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sclOen := true.B
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sdaOen := true.B
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sdaChk := false.B
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}
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is (s_bit_rd_a) {
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bitState := s_bit_rd_b
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sclOen := false.B
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sdaOen := true.B
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sdaChk := false.B
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}
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is (s_bit_rd_b) {
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bitState := s_bit_rd_c
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sclOen := true.B
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sdaOen := true.B
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sdaChk := false.B
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}
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is (s_bit_rd_c) {
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bitState := s_bit_rd_d
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sclOen := true.B
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sdaOen := true.B
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sdaChk := false.B
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}
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is (s_bit_rd_d) {
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bitState := s_bit_idle
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bitCmdAck := true.B
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sclOen := false.B
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sdaOen := true.B
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sdaChk := false.B
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}
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is (s_bit_wr_a) {
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bitState := s_bit_wr_b
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sclOen := false.B
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sdaOen := transmitBit
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sdaChk := false.B
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}
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is (s_bit_wr_b) {
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bitState := s_bit_wr_c
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sclOen := true.B
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sdaOen := transmitBit
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sdaChk := false.B
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}
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is (s_bit_wr_c) {
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bitState := s_bit_wr_d
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sclOen := true.B
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sdaOen := transmitBit
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sdaChk := true.B
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}
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is (s_bit_wr_d) {
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bitState := s_bit_idle
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bitCmdAck := true.B
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sclOen := false.B
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sdaOen := transmitBit
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sdaChk := false.B
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}
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}
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}
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}
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//////// Byte level ///////
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val load = Reg(init = Bool(false)) // load shift register
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val shift = Reg(init = Bool(false)) // shift shift register
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val cmdAck = Reg(init = Bool(false)) // also done
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val receivedAck = Reg(init = Bool(false)) // from I2C slave
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val go = (cmd.read | cmd.write | cmd.stop) & ~cmdAck // CHECK: why stop instead of start?
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val bitCnt = Reg(init = UInt(0, 3.W))
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when (load) {
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bitCnt := 0x7.U
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}
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.elsewhen (shift) {
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bitCnt := bitCnt - 1.U
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}
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val bitCntDone = !(bitCnt.orR)
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// receivedData is used as shift register directly
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when (load) {
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receivedData := transmitData
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}
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.otherwise {
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receivedData := Cat(receivedData, receivedBit)
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}
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val (s_byte_idle :: s_byte_start :: s_byte_read :: s_byte_write :: s_byte_ack :: s_byte_stop :: Nil) = Enum(UInt(), 6)
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val byteState = Reg(init = s_byte_idle)
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when (arbLost) {
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bitCmd := I2C_CMD_NOP
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transmitBit := false.B
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shift := false.B
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load := false.B
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cmdAck := false.B
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byteState := s_byte_idle
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receivedAck := false.B
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}
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.otherwise {
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transmitBit := receivedData(7)
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shift := false.B
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load := false.B
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cmdAck := false.B
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switch (byteState) {
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is (s_byte_idle) {
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when (go) {
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when (cmd.start) {
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byteState := s_byte_start
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bitCmd := I2C_CMD_START
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}
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.elsewhen (cmd.read) {
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byteState := s_byte_read
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bitCmd := I2C_CMD_READ
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}
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.elsewhen (cmd.write) {
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byteState := s_byte_write
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bitCmd := I2C_CMD_WRITE
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}
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.otherwise { // stop
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byteState := s_byte_stop
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bitCmd := I2C_CMD_STOP
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}
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load := true.B
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}
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}
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is (s_byte_start) {
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when (bitCmdAck) {
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when (cmd.read) {
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byteState := s_byte_read
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bitCmd := I2C_CMD_READ
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}
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.otherwise {
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byteState := s_byte_write
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bitCmd := I2C_CMD_WRITE
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}
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load := true.B
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}
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}
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is (s_byte_write) {
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when (bitCmdAck) {
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when (bitCntDone) {
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byteState := s_byte_ack
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bitCmd := I2C_CMD_READ
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}
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.otherwise {
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byteState := s_byte_write
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bitCmd := I2C_CMD_WRITE
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shift := true.B
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}
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}
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}
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is (s_byte_read) {
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when (bitCmdAck) {
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when (bitCntDone) {
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byteState := s_byte_ack
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bitCmd := I2C_CMD_WRITE
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}
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.otherwise {
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byteState := s_byte_read
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bitCmd := I2C_CMD_READ
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}
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shift := true.B
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transmitBit := cmd.ack
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}
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}
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is (s_byte_ack) {
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when (bitCmdAck) {
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when (cmd.stop) {
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byteState := s_byte_stop
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bitCmd := I2C_CMD_STOP
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}
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.otherwise {
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byteState := s_byte_idle
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bitCmd := I2C_CMD_NOP
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// generate command acknowledge signal
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cmdAck := true.B
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}
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// assign ack_out output to bit_controller_rxd (contains last received bit)
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receivedAck := receivedBit
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transmitBit := true.B
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}
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.otherwise {
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transmitBit := cmd.ack
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}
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}
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is (s_byte_stop) {
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when (bitCmdAck) {
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byteState := s_byte_idle
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bitCmd := I2C_CMD_NOP
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// assign ack_out output to bit_controller_rxd (contains last received bit)
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cmdAck := true.B
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}
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}
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}
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}
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//////// Top level ////////
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when (cmdAck || arbLost) {
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cmd.start := false.B // clear command bits when done
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cmd.stop := false.B // or when aribitration lost
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cmd.read := false.B
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cmd.write := false.B
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}
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cmd.irqAck := false.B // clear IRQ_ACK bit (essentially 1 cycle pulse b/c it is overwritten by regmap below)
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when (stopCond) {
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status.busy := false.B
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}
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.elsewhen (startCond) {
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status.busy := true.B
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}
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when (arbLost) {
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status.arbLost := true.B
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}
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.elsewhen (cmd.start) {
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status.arbLost := false.B
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}
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status.transferInProgress := cmd.read || cmd.write
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status.irqFlag := (cmdAck || arbLost || status.irqFlag) && !cmd.irqAck
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// hack
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val nextCmd = Wire(UInt(8.W))
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nextCmd := cmd.asUInt
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cmd := (new CommandBundle).fromBits(nextCmd)
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// Note that these are out of order.
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regmap(
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I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler_lo)),
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I2CCtrlRegs.prescaler_hi -> Seq(RegField(8, prescaler_hi)),
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I2CCtrlRegs.control -> Seq(RegField(8, control)),
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I2CCtrlRegs.data -> Seq(RegField(8, data)),
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I2CCtrlRegs.cmd_status -> Seq(RegField(8, cmd_status))
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I2CCtrlRegs.prescaler_lo -> Seq(RegField(8, prescaler.lo)),
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I2CCtrlRegs.prescaler_hi -> Seq(RegField(8, prescaler.hi)),
|
||||
I2CCtrlRegs.control -> control.elements.map{ case(name, e) => RegField(e.getWidth, e.asInstanceOf[UInt]) }.toSeq,
|
||||
I2CCtrlRegs.data -> Seq(RegField(8, r = RegReadFn(receivedData), w = RegWriteFn(transmitData))),
|
||||
I2CCtrlRegs.cmd_status -> Seq(RegField(8, r = RegReadFn(status.asUInt), w = RegWriteFn(nextCmd)))
|
||||
)
|
||||
|
||||
// tie off unused bits
|
||||
control.reserved := 0.U
|
||||
cmd.reserved := 0.U
|
||||
status.reserved := 0.U
|
||||
|
||||
interrupts(0) := status.irqFlag & control.intEn
|
||||
}
|
||||
|
||||
// Copied from UART.scala
|
||||
class Majority(in: Set[Bool]) {
|
||||
private val n = (in.size >> 1) + 1
|
||||
private val clauses = in.subsets(n).map(_.reduce(_ && _))
|
||||
val out = clauses.reduce(_ || _)
|
||||
}
|
||||
|
||||
|
||||
// Magic TL2 Incantation to create a TL2 Slave
|
||||
class TLI2C(c: I2CConfig)(implicit p: Parameters)
|
||||
extends TLRegisterRouter(c.address, interrupts = 1, beatBytes = p(PeripheryBusConfig).beatBytes)(
|
||||
|
||||
Loading…
Reference in New Issue
Block a user