riscv/sifive-blocks
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Merge pull request #17 from sifive/peripheral_options

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Make more peripherals "listable" to allow for 0 or more
This commit is contained in:
Megan Wachs 2017-06-09 22:07:43 -07:00 committed by GitHub
commit 27b00e177c
2 changed files with 26 additions and 13 deletions
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18
src/main/scala/devices/gpio/GPIOPeriphery.scala
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@ -10,23 +10,29 @@ import rocketchip.{
HasTopLevelNetworksModule HasTopLevelNetworksModule
} }
import uncore.tilelink2.TLFragmenter import uncore.tilelink2.TLFragmenter
import util.HeterogeneousBag
case object PeripheryGPIOKey extends Field[GPIOParams] case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
trait HasPeripheryGPIO extends HasTopLevelNetworks { trait HasPeripheryGPIO extends HasTopLevelNetworks {
val gpioParams = p(PeripheryGPIOKey) val gpioParams = p(PeripheryGPIOKey)
val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams)) val gpio = gpioParams map {params =>
gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params))
intBus.intnode := gpio.intnode gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := gpio.intnode
gpio
}
} }
trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle { trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripheryGPIO val outer: HasPeripheryGPIO
val gpio = new GPIOPortIO(outer.gpioParams) val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_)))
} }
trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule { trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule {
val outer: HasPeripheryGPIO val outer: HasPeripheryGPIO
val io: HasPeripheryGPIOBundle val io: HasPeripheryGPIOBundle
io.gpio <> outer.gpio.module.io.port (io.gpio zip outer.gpio) foreach { case (io, device) =>
io <> device.module.io.port
}
} }

21
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -37,23 +37,30 @@ trait HasPeripherySPIModule extends HasTopLevelNetworksModule {
} }
} }
case object PeripherySPIFlashKey extends Field[SPIFlashParams] case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
trait HasPeripherySPIFlash extends HasTopLevelNetworks { trait HasPeripherySPIFlash extends HasTopLevelNetworks {
val spiFlashParams = p(PeripherySPIFlashKey) val spiFlashParams = p(PeripherySPIFlashKey)
val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, spiFlashParams)) val qspi = spiFlashParams map { params =>
qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params))
qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node)) qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)
intBus.intnode := qspi.intnode qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node))
intBus.intnode := qspi.intnode
qspi
}
} }
trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle { trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle {
val outer: HasPeripherySPIFlash val outer: HasPeripherySPIFlash
val qspi = new SPIPortIO(outer.spiFlashParams) val qspi = HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_)))
} }
trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule { trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule {
val outer: HasPeripherySPIFlash val outer: HasPeripherySPIFlash
val io: HasPeripherySPIFlashBundle val io: HasPeripherySPIFlashBundle
io.qspi <> outer.qspi.module.io.port
(io.qspi zip outer.qspi) foreach { case (io, device) =>
io <> device.module.io.port
}
} }