From c89f163c0d045f454f8b0f813aa19047025e7dca Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 8 Jun 2017 16:25:20 -0700 Subject: [PATCH 1/3] GPIO: Make GPIO peripheral another listable one --- src/main/scala/devices/gpio/GPIOPeriphery.scala | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala index 20f8b5d..3c7a2ec 100644 --- a/src/main/scala/devices/gpio/GPIOPeriphery.scala +++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala @@ -11,22 +11,27 @@ import rocketchip.{ } import uncore.tilelink2.TLFragmenter -case object PeripheryGPIOKey extends Field[GPIOParams] +case object PeripheryGPIOKey extends Field[Seq[GPIOParams]] trait HasPeripheryGPIO extends HasTopLevelNetworks { val gpioParams = p(PeripheryGPIOKey) - val gpio = LazyModule(new TLGPIO(peripheryBusBytes, gpioParams)) - gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) - intBus.intnode := gpio.intnode + val gpio = gpioParams map {params => + val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params)) + gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) + intBus.intnode := gpio.intnode + gpio + } } trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle { val outer: HasPeripheryGPIO - val gpio = new GPIOPortIO(outer.gpioParams) + val gpio = HeterogeneousBag(outer.gpioParams(map(new GPIOPortIO(_)))) } trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule { val outer: HasPeripheryGPIO val io: HasPeripheryGPIOBundle - io.gpio <> outer.gpio.module.io.port + (io.gpio zip outer.gpio) foreach { case (io, device) => + io.gpio <> device.module.io.port + } } From 29226701a8ca7a5754b3d52cd9e99cf588782a75 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Thu, 8 Jun 2017 16:29:01 -0700 Subject: [PATCH 2/3] SPIFlash: make it listable --- src/main/scala/devices/spi/SPIPeriphery.scala | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index 1509ea7..2459b75 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -37,23 +37,30 @@ trait HasPeripherySPIModule extends HasTopLevelNetworksModule { } } -case object PeripherySPIFlashKey extends Field[SPIFlashParams] +case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]] trait HasPeripherySPIFlash extends HasTopLevelNetworks { val spiFlashParams = p(PeripherySPIFlashKey) - val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, spiFlashParams)) - qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) - qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node)) - intBus.intnode := qspi.intnode + val qspi = spiFlashParams map { params => + val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params)) + qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) + qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node)) + intBus.intnode := qspi.intnode + qspi + } } trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle { val outer: HasPeripherySPIFlash - val qspi = new SPIPortIO(outer.spiFlashParams) + val qspi = HeterogenousBag(outer.spiFlashParams.map(new SPIPortIO(_))) } trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule { val outer: HasPeripherySPIFlash val io: HasPeripherySPIFlashBundle - io.qspi <> outer.qspi.module.io.port + + (io.qspi zip outer.qspi) foreach { case (io, device) => + io.qspi <> device.module.io.port + } } + From 79f64de12cac914c0c195dc876f34adcaf15f7d5 Mon Sep 17 00:00:00 2001 From: Megan Wachs Date: Fri, 9 Jun 2017 13:53:22 -0700 Subject: [PATCH 3/3] peripheral_options: Actually compiles --- src/main/scala/devices/gpio/GPIOPeriphery.scala | 5 +++-- src/main/scala/devices/spi/SPIPeriphery.scala | 4 ++-- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/main/scala/devices/gpio/GPIOPeriphery.scala b/src/main/scala/devices/gpio/GPIOPeriphery.scala index 3c7a2ec..38fd20a 100644 --- a/src/main/scala/devices/gpio/GPIOPeriphery.scala +++ b/src/main/scala/devices/gpio/GPIOPeriphery.scala @@ -10,6 +10,7 @@ import rocketchip.{ HasTopLevelNetworksModule } import uncore.tilelink2.TLFragmenter +import util.HeterogeneousBag case object PeripheryGPIOKey extends Field[Seq[GPIOParams]] @@ -25,13 +26,13 @@ trait HasPeripheryGPIO extends HasTopLevelNetworks { trait HasPeripheryGPIOBundle extends HasTopLevelNetworksBundle { val outer: HasPeripheryGPIO - val gpio = HeterogeneousBag(outer.gpioParams(map(new GPIOPortIO(_)))) + val gpio = HeterogeneousBag(outer.gpioParams.map(new GPIOPortIO(_))) } trait HasPeripheryGPIOModule extends HasTopLevelNetworksModule { val outer: HasPeripheryGPIO val io: HasPeripheryGPIOBundle (io.gpio zip outer.gpio) foreach { case (io, device) => - io.gpio <> device.module.io.port + io <> device.module.io.port } } diff --git a/src/main/scala/devices/spi/SPIPeriphery.scala b/src/main/scala/devices/spi/SPIPeriphery.scala index 2459b75..daa0a9f 100644 --- a/src/main/scala/devices/spi/SPIPeriphery.scala +++ b/src/main/scala/devices/spi/SPIPeriphery.scala @@ -52,7 +52,7 @@ trait HasPeripherySPIFlash extends HasTopLevelNetworks { trait HasPeripherySPIFlashBundle extends HasTopLevelNetworksBundle { val outer: HasPeripherySPIFlash - val qspi = HeterogenousBag(outer.spiFlashParams.map(new SPIPortIO(_))) + val qspi = HeterogeneousBag(outer.spiFlashParams.map(new SPIPortIO(_))) } trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule { @@ -60,7 +60,7 @@ trait HasPeripherySPIFlashModule extends HasTopLevelNetworksModule { val io: HasPeripherySPIFlashBundle (io.qspi zip outer.qspi) foreach { case (io, device) => - io.qspi <> device.module.io.port + io <> device.module.io.port } }