riscv/sifive-blocks
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Merge remote-tracking branch 'origin/master' into typed_pad_ctrl

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This commit is contained in:
Megan Wachs 2017-07-24 09:17:53 -07:00
commit 0a80d1987d
10 changed files with 71 additions and 76 deletions
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11
src/main/scala/devices/gpio/GPIOPeriphery.scala
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@ -3,19 +3,18 @@ package sifive.blocks.devices.gpio
import Chisel._ import Chisel._
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.TLFragmenter
import freechips.rocketchip.util.HeterogeneousBag import freechips.rocketchip.util.HeterogeneousBag
case object PeripheryGPIOKey extends Field[Seq[GPIOParams]] case object PeripheryGPIOKey extends Field[Seq[GPIOParams]]
trait HasPeripheryGPIO extends HasSystemNetworks { trait HasPeripheryGPIO extends HasPeripheryBus with HasInterruptBus {
val gpioParams = p(PeripheryGPIOKey) val gpioParams = p(PeripheryGPIOKey)
val gpios = gpioParams map { params => val gpios = gpioParams map { params =>
val gpio = LazyModule(new TLGPIO(peripheryBusBytes, params)) val gpio = LazyModule(new TLGPIO(pbus.beatBytes, params))
gpio.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) gpio.node := pbus.toVariableWidthSlaves
intBus.intnode := gpio.intnode ibus.fromSync := gpio.intnode
gpio gpio
} }
} }

11
src/main/scala/devices/i2c/I2CPeriphery.scala
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@ -3,18 +3,17 @@ package sifive.blocks.devices.i2c
import Chisel._ import Chisel._
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.{HasSystemNetworks}
import freechips.rocketchip.tilelink.TLFragmenter
case object PeripheryI2CKey extends Field[Seq[I2CParams]] case object PeripheryI2CKey extends Field[Seq[I2CParams]]
trait HasPeripheryI2C extends HasSystemNetworks { trait HasPeripheryI2C extends HasPeripheryBus {
val i2cParams = p(PeripheryI2CKey) val i2cParams = p(PeripheryI2CKey)
val i2c = i2cParams map { params => val i2c = i2cParams map { params =>
val i2c = LazyModule(new TLI2C(peripheryBusBytes, params)) val i2c = LazyModule(new TLI2C(pbus.beatBytes, params))
i2c.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) i2c.node := pbus.toVariableWidthSlaves
intBus.intnode := i2c.intnode ibus.fromSync := i2c.intnode
i2c i2c
} }
} }

23
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -3,22 +3,25 @@ package sifive.blocks.devices.mockaon
import Chisel._ import Chisel._
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.{HasSystemNetworks, HasCoreplexRISCVPlatform} import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource}
import freechips.rocketchip.tilelink.{IntXing, TLAsyncCrossingSource, TLFragmenter}
import freechips.rocketchip.util.ResetCatchAndSync import freechips.rocketchip.util.ResetCatchAndSync
case object PeripheryMockAONKey extends Field[MockAONParams] case object PeripheryMockAONKey extends Field[MockAONParams]
trait HasPeripheryMockAON extends HasSystemNetworks with HasCoreplexRISCVPlatform { trait HasPeripheryMockAON extends HasPeripheryBus
with HasInterruptBus
with HasPeripheryClint
with HasPeripheryDebug {
// We override the clock & Reset here so that all synchronizers, etc // We override the clock & Reset here so that all synchronizers, etc
// are in the proper clock domain. // are in the proper clock domain.
val mockAONParams= p(PeripheryMockAONKey) val mockAONParams= p(PeripheryMockAONKey)
val aon = LazyModule(new MockAONWrapper(peripheryBusBytes, mockAONParams)) val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
val aon_int = LazyModule(new IntXing) aon.node := pbus.toAsyncVariableWidthSlaves(sync = 3)
aon.node := TLAsyncCrossingSource()(TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node)) ibus.fromAsync := aon.intnode
aon_int.intnode := aon.intnode
intBus.intnode := aon_int.intnode
} }
trait HasPeripheryMockAONBundle { trait HasPeripheryMockAONBundle {
@ -39,7 +42,7 @@ trait HasPeripheryMockAONModuleImp extends LazyMultiIOModuleImp with HasPeripher
outer.aon.module.clock := Bool(false).asClock outer.aon.module.clock := Bool(false).asClock
outer.aon.module.reset := Bool(true) outer.aon.module.reset := Bool(true)
outer.coreplex.module.io.rtcToggle := outer.aon.module.io.rtc.asUInt.toBool outer.clint.module.io.rtcTick := outer.aon.module.io.rtc.asUInt.toBool
outer.aon.module.io.ndreset := outer.coreplex.module.io.ndreset outer.aon.module.io.ndreset := outer.debug.module.io.ctrl.ndreset
} }

13
src/main/scala/devices/pwm/PWMPeriphery.scala
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@ -3,11 +3,10 @@ package sifive.blocks.devices.pwm
import Chisel._ import Chisel._
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink.TLFragmenter
import freechips.rocketchip.util.HeterogeneousBag import freechips.rocketchip.util.HeterogeneousBag
import sifive.blocks.devices.pinctrl.{PinCtrl, Pin} import sifive.blocks.devices.pinctrl.{Pin}
class PWMPortIO(val c: PWMParams) extends Bundle { class PWMPortIO(val c: PWMParams) extends Bundle {
val port = Vec(c.ncmp, Bool()).asOutput val port = Vec(c.ncmp, Bool()).asOutput
@ -30,12 +29,12 @@ class PWMPins[T <: Pin] (pingen: ()=> T, val c: PWMParams) extends Bundle {
case object PeripheryPWMKey extends Field[Seq[PWMParams]] case object PeripheryPWMKey extends Field[Seq[PWMParams]]
trait HasPeripheryPWM extends HasSystemNetworks { trait HasPeripheryPWM extends HasPeripheryBus with HasInterruptBus {
val pwmParams = p(PeripheryPWMKey) val pwmParams = p(PeripheryPWMKey)
val pwms = pwmParams map { params => val pwms = pwmParams map { params =>
val pwm = LazyModule(new TLPWM(peripheryBusBytes, params)) val pwm = LazyModule(new TLPWM(pbus.beatBytes, params))
pwm.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) pwm.node := pbus.toVariableWidthSlaves
intBus.intnode := pwm.intnode ibus.fromSync := pwm.intnode
pwm pwm
} }
} }

23
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -3,19 +3,19 @@ package sifive.blocks.devices.spi
import Chisel._ import Chisel._
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule,LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks import freechips.rocketchip.tilelink.{TLFragmenter}
import freechips.rocketchip.tilelink.{TLFragmenter,TLWidthWidget}
import freechips.rocketchip.util.HeterogeneousBag import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]] case object PeripherySPIKey extends Field[Seq[SPIParams]]
trait HasPeripherySPI extends HasSystemNetworks { trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
val spiParams = p(PeripherySPIKey) val spiParams = p(PeripherySPIKey)
val spis = spiParams map { params => val spis = spiParams map { params =>
val spi = LazyModule(new TLSPI(peripheryBusBytes, params)) val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
spi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) spi.rnode := pbus.toVariableWidthSlaves
intBus.intnode := spi.intnode ibus.fromSync := spi.intnode
spi spi
} }
} }
@ -36,13 +36,13 @@ trait HasPeripherySPIModuleImp extends LazyMultiIOModuleImp with HasPeripherySPI
case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]] case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
trait HasPeripherySPIFlash extends HasSystemNetworks { trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
val spiFlashParams = p(PeripherySPIFlashKey) val spiFlashParams = p(PeripherySPIFlashKey)
val qspis = spiFlashParams map { params => val qspis = spiFlashParams map { params =>
val qspi = LazyModule(new TLSPIFlash(peripheryBusBytes, params)) val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) qspi.rnode := pbus.toVariableWidthSlaves
qspi.fnode := TLFragmenter(1, cacheBlockBytes)(TLWidthWidget(peripheryBusBytes)(peripheryBus.node)) qspi.fnode := TLFragmenter(1, pbus.blockBytes)(pbus.toFixedWidthSlaves)
intBus.intnode := qspi.intnode ibus.fromSync := qspi.intnode
qspi qspi
} }
} }
@ -60,4 +60,3 @@ trait HasPeripherySPIFlashModuleImp extends LazyMultiIOModuleImp with HasPeriphe
io <> device.module.io.port io <> device.module.io.port
} }
} }

4
src/main/scala/devices/uart/UART.scala
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@ -2,8 +2,8 @@
package sifive.blocks.devices.uart package sifive.blocks.devices.uart
import Chisel._ import Chisel._
import freechips.rocketchip.chip.RTCPeriod
import freechips.rocketchip.config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex.RTCPeriod
import freechips.rocketchip.diplomacy.DTSTimebase import freechips.rocketchip.diplomacy.DTSTimebase
import freechips.rocketchip.regmapper._ import freechips.rocketchip.regmapper._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
@ -205,7 +205,7 @@ trait HasUARTTopModuleContents extends Module with HasUARTParameters with HasReg
val rxm = Module(new UARTRx(params)) val rxm = Module(new UARTRx(params))
val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries)) val rxq = Module(new Queue(rxm.io.out.bits, uartNRxEntries))
val divinit = p(DTSTimebase) * p(RTCPeriod) / 115200 val divinit = p(DTSTimebase) * BigInt(p(RTCPeriod).getOrElse(1)) / 115200
val div = Reg(init = UInt(divinit, uartDivisorBits)) val div = Reg(init = UInt(divinit, uartDivisorBits))
private val stopCountBits = log2Up(uartStopBits) private val stopCountBits = log2Up(uartStopBits)

13
src/main/scala/devices/uart/UARTPeriphery.scala
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@ -4,20 +4,19 @@ package sifive.blocks.devices.uart
import Chisel._ import Chisel._
import chisel3.experimental.{withClockAndReset} import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks import sifive.blocks.devices.pinctrl.{Pin}
import freechips.rocketchip.tilelink.TLFragmenter
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
import sifive.blocks.util.ShiftRegisterInit import sifive.blocks.util.ShiftRegisterInit
case object PeripheryUARTKey extends Field[Seq[UARTParams]] case object PeripheryUARTKey extends Field[Seq[UARTParams]]
trait HasPeripheryUART extends HasSystemNetworks { trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
val uartParams = p(PeripheryUARTKey) val uartParams = p(PeripheryUARTKey)
val uarts = uartParams map { params => val uarts = uartParams map { params =>
val uart = LazyModule(new TLUART(peripheryBusBytes, params)) val uart = LazyModule(new TLUART(pbus.beatBytes, params))
uart.node := TLFragmenter(peripheryBusBytes, cacheBlockBytes)(peripheryBus.node) uart.node := pbus.toVariableWidthSlaves
intBus.intnode := uart.intnode ibus.fromSync := uart.intnode
uart uart
} }
} }

3
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala
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@ -4,9 +4,8 @@ package sifive.blocks.devices.xilinxvc707mig
import Chisel._ import Chisel._
import chisel3.experimental.{Analog,attach} import chisel3.experimental.{Analog,attach}
import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.chip._
import freechips.rocketchip.config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex.CacheBlockBytes import freechips.rocketchip.coreplex._
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig} import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}

17
src/main/scala/devices/xilinxvc707mig/XilinxVC707MIGPeriphery.scala
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@ -2,27 +2,28 @@
package sifive.blocks.devices.xilinxvc707mig package sifive.blocks.devices.xilinxvc707mig
import Chisel._ import Chisel._
import freechips.rocketchip.coreplex.HasMemoryBus
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
trait HasPeripheryXilinxVC707MIG extends HasSystemNetworks { trait HasMemoryXilinxVC707MIG extends HasMemoryBus {
val module: HasPeripheryXilinxVC707MIGModuleImp val module: HasMemoryXilinxVC707MIGModuleImp
val xilinxvc707mig = LazyModule(new XilinxVC707MIG) val xilinxvc707mig = LazyModule(new XilinxVC707MIG)
require(nMemoryChannels == 1, "Coreplex must have 1 master memory port") require(nMemoryChannels == 1, "Coreplex must have 1 master memory port")
xilinxvc707mig.node := mem(0).node xilinxvc707mig.node := memBuses.head.toDRAMController
} }
trait HasPeripheryXilinxVC707MIGBundle { trait HasMemoryXilinxVC707MIGBundle {
val xilinxvc707mig: XilinxVC707MIGIO val xilinxvc707mig: XilinxVC707MIGIO
def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) { def connectXilinxVC707MIGToPads(pads: XilinxVC707MIGPads) {
pads <> xilinxvc707mig pads <> xilinxvc707mig
} }
} }
trait HasPeripheryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp trait HasMemoryXilinxVC707MIGModuleImp extends LazyMultiIOModuleImp
with HasPeripheryXilinxVC707MIGBundle { with HasMemoryXilinxVC707MIGBundle {
val outer: HasPeripheryXilinxVC707MIG val outer: HasMemoryXilinxVC707MIG
val xilinxvc707mig = IO(new XilinxVC707MIGIO) val xilinxvc707mig = IO(new XilinxVC707MIGIO)
xilinxvc707mig <> outer.xilinxvc707mig.module.io.port xilinxvc707mig <> outer.xilinxvc707mig.module.io.port

23
src/main/scala/devices/xilinxvc707pciex1/XilinxVC707PCIeX1Periphery.scala
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@ -2,31 +2,28 @@
package sifive.blocks.devices.xilinxvc707pciex1 package sifive.blocks.devices.xilinxvc707pciex1
import Chisel._ import Chisel._
import freechips.rocketchip.coreplex.{HasInterruptBus, HasSystemBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp} import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import freechips.rocketchip.chip.HasSystemNetworks
import freechips.rocketchip.tilelink._
trait HasPeripheryXilinxVC707PCIeX1 extends HasSystemNetworks { trait HasSystemXilinxVC707PCIeX1 extends HasSystemBus with HasInterruptBus {
val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1) val xilinxvc707pcie = LazyModule(new XilinxVC707PCIeX1)
private val intXing = LazyModule(new IntXing)
fsb.node := TLAsyncCrossingSink()(xilinxvc707pcie.master) sbus.fromAsyncFIFOMaster() := xilinxvc707pcie.master
xilinxvc707pcie.slave := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node)) xilinxvc707pcie.slave := sbus.toAsyncFixedWidthSlaves()
xilinxvc707pcie.control := TLAsyncCrossingSource()(TLWidthWidget(socBusConfig.beatBytes)(socBus.node)) xilinxvc707pcie.control := sbus.toAsyncFixedWidthSlaves()
intBus.intnode := intXing.intnode ibus.fromAsync := xilinxvc707pcie.intnode
intXing.intnode := xilinxvc707pcie.intnode
} }
trait HasPeripheryXilinxVC707PCIeX1Bundle { trait HasSystemXilinxVC707PCIeX1Bundle {
val xilinxvc707pcie: XilinxVC707PCIeX1IO val xilinxvc707pcie: XilinxVC707PCIeX1IO
def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) { def connectXilinxVC707PCIeX1ToPads(pads: XilinxVC707PCIeX1Pads) {
pads <> xilinxvc707pcie pads <> xilinxvc707pcie
} }
} }
trait HasPeripheryXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp trait HasSystemXilinxVC707PCIeX1ModuleImp extends LazyMultiIOModuleImp
with HasPeripheryXilinxVC707PCIeX1Bundle { with HasSystemXilinxVC707PCIeX1Bundle {
val outer: HasPeripheryXilinxVC707PCIeX1 val outer: HasSystemXilinxVC707PCIeX1
val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO) val xilinxvc707pcie = IO(new XilinxVC707PCIeX1IO)
xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port xilinxvc707pcie <> outer.xilinxvc707pcie.module.io.port