58 lines
1.7 KiB
Scala
58 lines
1.7 KiB
Scala
// See LICENSE for license details.
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package sifive.blocks.devices.uart
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import Chisel._
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import chisel3.experimental.{withClockAndReset}
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import freechips.rocketchip.config.Field
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import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
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import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
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import sifive.blocks.devices.pinctrl.{Pin}
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import sifive.blocks.util.ShiftRegisterInit
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case object PeripheryUARTKey extends Field[Seq[UARTParams]]
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trait HasPeripheryUART extends HasPeripheryBus with HasInterruptBus {
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val uartParams = p(PeripheryUARTKey)
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val uarts = uartParams map { params =>
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val uart = LazyModule(new TLUART(pbus.beatBytes, params))
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uart.node := pbus.toVariableWidthSlaves
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ibus.fromSync := uart.intnode
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uart
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}
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}
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trait HasPeripheryUARTBundle {
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val uart: Vec[UARTPortIO]
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def tieoffUARTs(dummy: Int = 1) {
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uart.foreach { _.rxd := UInt(1) }
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}
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}
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trait HasPeripheryUARTModuleImp extends LazyMultiIOModuleImp with HasPeripheryUARTBundle {
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val outer: HasPeripheryUART
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val uart = IO(Vec(outer.uartParams.size, new UARTPortIO))
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(uart zip outer.uarts).foreach { case (io, device) =>
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io <> device.module.io.port
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}
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}
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class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
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val rxd = pingen()
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val txd = pingen()
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override def cloneType: this.type =
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this.getClass.getConstructors.head.newInstance(pingen).asInstanceOf[this.type]
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def fromUARTPort(uart: UARTPortIO, clock: Clock, reset: Bool, syncStages: Int = 0) {
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withClockAndReset(clock, reset) {
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txd.outputPin(uart.txd)
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val rxd_t = rxd.inputPin()
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uart.rxd := ShiftRegisterInit(rxd_t, syncStages, Bool(true))
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}
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}
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}
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