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periphery: bus api update (#50)

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This commit is contained in:
Henry Cook
2018-03-01 01:15:02 -08:00
committed by GitHub
parent 3dee152775
commit 00fbfb6dd8
8 changed files with 44 additions and 49 deletions
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26
src/main/scala/devices/spi/SPIPeriphery.scala
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@ -3,18 +3,19 @@ package sifive.blocks.devices.spi
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.diplomacy.{LazyModule,LazyModuleImp,BufferParams}
import freechips.rocketchip.tilelink.{TLFragmenter,TLBuffer}
import freechips.rocketchip.util.HeterogeneousBag
case object PeripherySPIKey extends Field[Seq[SPIParams]]
trait HasPeripherySPI extends HasPeripheryBus with HasInterruptBus {
trait HasPeripherySPI { this: BaseSubsystem =>
val spiParams = p(PeripherySPIKey)
val spis = spiParams map { params =>
val spi = LazyModule(new TLSPI(pbus.beatBytes, params))
spi.rnode := pbus.toVariableWidthSlaves
val spis = spiParams.zipWithIndex.map { case(params, i) =>
val name = Some(s"spi_$i")
val spi = LazyModule(new TLSPI(pbus.beatBytes, params)).suggestName(name)
pbus.toVariableWidthSlave(name) { spi.rnode }
ibus.fromSync := spi.intnode
spi
}
@ -36,15 +37,16 @@ trait HasPeripherySPIModuleImp extends LazyModuleImp with HasPeripherySPIBundle
case object PeripherySPIFlashKey extends Field[Seq[SPIFlashParams]]
trait HasPeripherySPIFlash extends HasPeripheryBus with HasInterruptBus {
trait HasPeripherySPIFlash { this: BaseSubsystem =>
val spiFlashParams = p(PeripherySPIFlashKey)
val qspis = spiFlashParams map { params =>
val qspis = spiFlashParams.zipWithIndex.map { case(params, i) =>
val name = Some(s"qspi_$i")
val qspi = LazyModule(new TLSPIFlash(pbus.beatBytes, params))
qspi.rnode := pbus.toVariableWidthSlaves
(qspi.fnode
:= TLFragmenter(1, pbus.blockBytes)
:= TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
:= pbus.toFixedWidthSlaves)
pbus.toVariableWidthSlave(name) { qspi.rnode }
qspi.fnode := pbus.toFixedWidthSlave(name) {
TLFragmenter(1, pbus.blockBytes) :=
TLBuffer(BufferParams(params.fBufferDepth), BufferParams.none)
}
ibus.fromSync := qspi.intnode
qspi
}