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periphery: bus api update (#50)

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This commit is contained in:
Henry Cook
2018-03-01 01:15:02 -08:00
committed by GitHub
parent 3dee152775
commit 00fbfb6dd8
8 changed files with 44 additions and 49 deletions
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16
src/main/scala/devices/mockaon/MockAONPeriphery.scala
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@ -3,26 +3,22 @@ package sifive.blocks.devices.mockaon
import Chisel._
import freechips.rocketchip.config.Field
import freechips.rocketchip.util.SynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
import freechips.rocketchip.devices.debug.HasPeripheryDebug
import freechips.rocketchip.devices.tilelink.HasPeripheryClint
import freechips.rocketchip.devices.tilelink.HasPeripheryCLINT
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util.ResetCatchAndSync
import freechips.rocketchip.subsystem.BaseSubsystem
import freechips.rocketchip.tilelink.{TLAsyncCrossingSource}
import freechips.rocketchip.util.{ResetCatchAndSync, SynchronizerShiftReg}
case object PeripheryMockAONKey extends Field[MockAONParams]
trait HasPeripheryMockAON extends HasPeripheryBus
with HasInterruptBus
with HasPeripheryClint
with HasPeripheryDebug {
trait HasPeripheryMockAON extends HasPeripheryCLINT with HasPeripheryDebug { this: BaseSubsystem =>
// We override the clock & Reset here so that all synchronizers, etc
// are in the proper clock domain.
val mockAONParams= p(PeripheryMockAONKey)
val aon = LazyModule(new MockAONWrapper(pbus.beatBytes, mockAONParams))
aon.node := TLAsyncCrossingSource() := pbus.toVariableWidthSlaves
pbus.toVariableWidthSlave(Some("aon")) { aon.node := TLAsyncCrossingSource() }
ibus.fromSync := IntSyncCrossingSink() := aon.intnode
}